MEMORY CONTROLLER AND DATA MANAGEMENT METHOD THEREOF

• US 20140164687A1
• Filed: 02/11/2014
• Published: 06/12/2014
• Est. Priority Date: 08/12/2011
• Status: Active Grant

• Current Assignee: Ajou University Industry
• Original Assignee: Ajou University Industry
• Inventors: Kwon, Se Jin, Chung, Tae Sun, Keam, Byeong Kuk, Jin, Rize
• Granted Patent: US 9,304,905 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

The present invention provides a flash memory controller for mapping the logical addresses to the physical addresses of memory including a plurality of blocks, each having a plurality of pages, wherein the memory controller includes a processor. The processor includes hot page decision unit and an address translation unit. The hot page decision unit classifies pages in each block into hot pages and cold pages based on a predetermined criterion. When there is a plurality of the classified hot pages, the address translation unit respectively arranges the classified hot pages in different target blocks.

In accordance with this configuration, upon performing a merge operation, hot pages and cold pages are determined, and the hot pages are respectively distributed to empty blocks, so that concentration of an erase operation on a specific physical block may be avoided, thus wear-leveling may be performed more efficiently.

Claims

1. A memory controller for managing correspondence between logical addresses and physical addresses of memory including a plurality of blocks, each having a plurality of pages, comprising:

a processor configured to;

classify pages in each block into hot pages and cold pages based on a predetermined criterion; and

respectively arrange the classified hot pages in different target blocks when there is a plurality of the classified hot pages.

2. The memory controller of claim 1, wherein the predetermined criterion includes at least one of update frequency of each page or attributes of data to be written to the page.

3. The memory controller of claim 1, wherein the processor is further configured to:

if the classified hot pages are respectively arranged in the target blocks, sequentially arrange the classified cold pages in remaining pages of the target blocks.

4. The memory controller of claim 1, wherein the processor is further configured to:

if a number of the classified hot pages is one or less, copy data stored in at least one existing physical block corresponding to a logical block to a target block, define the target block as an information block;

erase the at least one existing physical block; and

define the erased physical block as an empty block.

5. The memory controller of claim 1, wherein the processor is further configured to:

if a number of the classified hot pages is more than one, select at least one victim block, wherein at least one victim block does not include hot pages;

divide cold pages of the victim block into a plurality of sets of cold pages; and

arrange the plurality of sets of cold pages in the plurality of target blocks.

6. The memory controller of claim 5, wherein the processor is further configured to:

select a block, in which a number of erasures is equal to or less than a predetermined reference value, or is a least value, as the victim block.

7. The memory controller of claim 1, wherein the processor is further configured to:

record page addresses of pages, previously located in a first physical block corresponding to an existing logical block and newly located in a second physical block different from the first physical block, in an additional address mapping table.

8. A data management method of a memory controller for managing correspondence between logical addresses and physical addresses of memory including a plurality of blocks, each having a plurality of pages, comprising:

classifying, by a processor, pages in each block into hot pages and cold pages based on a predetermined criterion; and

respectively arranging, by the processor, the classified hot pages in different target blocks when there is a plurality of classified hot pages.

9. The data management method of claim 8, wherein the predetermined criterion includes at least one of update frequency of each page or attributes of data to be written to the page.

10. The data management method of claim 8, further comprising:

if the classified hot pages are respectively arranged in the target blocks, sequentially arranging, by the processor, the classified cold pages in remaining pages of the target blocks.

11. The data management method of claim 8, further comprising:

if a number of the classified hot pages is more than one, selecting, by the processor, a victim block, in which a number of erasures is equal to or less than a predetermined reference value or is a least value, from among blocks which do not include hot pages;

dividing, by the processor, cold pages of the victim block into a plurality of sets of cold pages; and

arranging, by the processor, the plurality of sets of cold pages in the plurality of target blocks.

12. The data management method of claim 8, further comprising:

recording, by the processor, page addresses of pages, previously located in a first physical block corresponding to an existing logical block and newly located in a second physical block different from the first physical, in an additional address mapping table.

13. A non-transitory computer-readable storage medium containing executable program instructions executed by a processor that stores a program for executing a method of managing a data of a memory controller for managing correspondence between logical addresses and physical addresses of memory including a plurality of blocks, each having a plurality of pages, comprising:

program instructions that classify pages in each block into hot pages and cold pages based on a predetermined criterion; and

program instructions that respectively arrange the classified hot pages in different target blocks when there is a plurality of classified hot pages.