SYSTEM ON CHIP TO PERFORM A SECURE BOOT, AN IMAGE FORMING APPARATUS USING THE SAME, AND METHOD THEREOF

• US 20140164725A1
• Filed: 12/06/2013
• Published: 06/12/2014
• Est. Priority Date: 12/06/2012
• Status: Active Grant

• Current Assignee: HP Printing Korea Co., Ltd. (HP Inc.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Jong-seung, JUN, Jin-hwi, JANG, Tae-hong
• Granted Patent: US 9,881,161 B2
• Time in Patent Office: Days
• US Class Current: 711/163
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/84 output devices, e.g. displays or monitors
• CPC Class Codes: G06F 2221/2105 Dual mode as a secondary aspect
• CPC Class Codes: G06F 2221/2153 Using hardware token as a secondary aspect

Abstract

A system on chip is provided. The system on chip includes a first memory to store a plurality of encryption keys, a second memory, a third memory to store an encryption key setting value, and a CPU to decrypt encrypted data which is stored in an external non-volatile memory using an encryption key corresponding to the encryption key setting value from among the plurality of encryption keys, to store the decrypted data in the second memory, and to perform a boot using data stored in the second memory. Accordingly, security of a boot operation can be improved.

Claims

1. A system on chip comprising:

a first memory to store a plurality of encryption keys are stored;

a second memory;

a third memory to store an encryption key setting value is stored; and

a CPU to decrypt encrypted data which is stored in an external non-volatile memory using an encryption key corresponding to the encryption key setting value from among the plurality of encryption keys, to store the decrypted data in the second memory, and to perform a boot using data stored in the second memory.

2. The system on chip as claimed in claim 1, wherein initialization data is stored in the first memory separately from the plurality of encryption keys,

wherein the CPU performs initialization using the initialization data and decrypts the encrypted data.

3. The system on chip as claimed in claim 2, further comprising a first circuit to restrict access to CPU via an external port for a predetermined time.

4. The system on chip as claimed in claim 3, wherein, when power is switched on, the first circuit outputs a disable signal to disable the access to the CPU, and, when at least the decryption and authentication of the decrypted data is completed, the first circuit outputs an enable signal to enable the access to the CPU.

5. The system on chip as claimed in claim 4, wherein the first circuit comprises a first register,

wherein, when the at least the decryption and authentication of the decrypted data is completed, the CPU changes a storage value of the first register.

6. The system on chip as claimed in claim 5, further comprising a second circuit and a third circuit to control access to the first memory.

7. The system on chip as claimed in claim 6, wherein the second circuit comprises a second register, and the third circuit comprises a third register,

wherein, when the at least the decryption and authentication of the decrypted data is completed, the CPU stores a control value to disable access to the first memory in the second register, and stores a control value to change the access to the first memory to access to the second memory in the third register.

8. The system on chip as claimed in claim 1, wherein the CPU executes an infinite loop when the decryption fails.

9. The system on chip as claimed in claim 1, wherein, when power is switched on, the CPU identifies a memory that is designated by a setting value stored in the third memory or an external pin, and, when the first memory is designated, the CPU performs secure boot using the encrypted data, and, when the second memory is designated, the CPU performs normal boot using non-encrypted data which is stored in the non volatile memory.

10. The system on chip as claimed in claim 1, wherein the first memory is a mask Read Only Memory (ROM) or a one-time programmable (OTP) ROM,

wherein the second memory is a static random access memory (SRAM),

wherein the third memory is an electrical fuse (EFUSE) memory.

11. The system on chip as claimed in claim 1, further comprising:

a first memory controller to control access to the first memory;

a second memory controller to control access to the second memory;

a bus; and

a switching unit to connect selectively one of the first memory controller and the second memory controller with the bus according to the operation state of the CPU.

12. The system on chip as claimed in claim 11, wherein the first memory controller comprises a register where an access control value on the first memory is registered,

wherein the switching unit selectively connects one of the first memory controller and the second memory controller with the bus according to the access control value,

wherein the CPU disables access to the first memory by changing the access control value when the CPU'"'"'s use of the first memory is completed.

13. The system on chip as claimed in claim 1, further comprising:

a memory controller communicatively coupled to the CPU, including at least one switch to select a connection state with the external memory,

wherein the memory controller selectively outputs a writing signal received from the CPU to the external memory according to a result of a comparison between a first key value and a second key value.

14. The system on chip as claimed in claim 13, wherein the memory controller controls the at least one switch to select the connection state so as to output the writing signal to the external memory when the first key value and the second key value are the same.

15. The system on chip as claimed in claim 13, wherein the memory controller controls the at least one switch so as to disable the connection to the external memory so as to prevent the writing signal from being output to the external memory.

16. The system on chip as claimed in claim 15, wherein the memory controller controls a read operation of the external memory even when the memory controller is preventing the writing signal from being output to the external memory.

17. The system on chip as claimed in claim 13, wherein the at least one switch includes a first switch and a second switch, with the memory controller to control the first switch so as to control a read operation of the external memory, and the second switch to control a connection with the second switch so as to control the output of the writing signal to the external memory.

18. The system on chip as claimed in claim 1, further comprising;

a code generating unit to generate a software code, wherein the CPU performs initializing by using the software code.

19. The system on chip as claimed in claim 18, wherein the code generating unit comprises:

an address decoder to receive an address from the CPU and to decode the address;

a plurality of registers; and

a multiplexer to generate the software code by selectively reading register values stored in the plurality of registers according to an address decoded in the address decoder, and by combining the register values.

20. The system on chip a claimed in claim 18, wherein the code generating unit comprises:

an address decoder to receive an address from the CPU and to decode the address;

a first generating unit to generate an instruction address from the address decoded in the address decoder;

a plurality of instruction registers to be divided into a plurality of groups;

a plurality of instruction multiplexers to read selectively a register value from the plurality of instruction registers according to the instruction address;

a code formatter to generate a code by combining values read in the plurality of instruction multiplexers;

a second generating unit to generate a data address from the address decoded in the address decoder;

a plurality of data registers;

a data multiplexer to read selectively register values from the plurality of data registers according to the data address and to combine the read values; and

a multiplexer to generate the software code by combining a code generated in the code formatter with data combined in the second multiplexer.

21. The system on chip as claimed in claim 1, further comprising;

a memory controller to control access to the external non volatile memory,

wherein the memory controller, when a writing signal on the external non volatile memory and a first key value are transmitted from the CPU, compares the first key value with a pre-stored second key value, and when the values are the same with each other, performs a writing operation on the external non volatile memory according to the writing signal.

22. The system on chip as claimed in claim 21, wherein when the first key value and the pre-stored second key value are different from one another, the memory controller blocks a writing operation to the external non volatile memory.

23. The system on chip as claimed in claim 21, wherein the memory controller comprises:

a signal transferring unit to store the first key value transmitted from the CPU;

a key value storage to store the second key value;

a comparing unit to compare the first key value stored in the signal transferring unit with the second key value stored in the key value storage; and

a signal processor to output the writing signal transmitted from the CPU to the external non volatile memory according to the compared result.

24. An image forming apparatus comprising:

a consumable unit in which a Customer Replaceable Unit Monitoring (CRUM) chip is mounted; and

a controller to perform an image forming job using the consumable unit and to update data recorded on the CRUM chip according to the image forming job,

wherein the controller comprises;

a non-volatile memory to record encrypted data; and

a system on chip to perform a secure boot using the encrypted data when the image forming apparatus is turned on, and to control the image forming apparatus according to a user command when the secure boot is completed.

25. The image forming apparatus as claimed in claim 24, wherein the system on chip comprises:

a first memory to store a plurality of encryption keys;

a second memory;

a third memory to store an encryption key setting value is stored; and

a CPU to decrypt data which is stored in the non-volatile memory using an encryption key corresponding to the encryption key setting value from among the plurality of encryption keys, to store the decrypted data in the second memory, and to perform boot using data stored in the second memory.

26. The image forming apparatus as claimed in claim 25, wherein initialization data is stored in the first memory separately from the plurality of encryption keys,

wherein the CPU performs initialization using the initialization data and then decrypts the encrypted data.

27. The image forming apparatus as claimed in claim 26, wherein, when a boot event has occurred, the system on chip restricts access to CPU via an external port for a predetermined time.

28. The image forming apparatus as claimed in claim 27, wherein the system on chip further comprises a first circuit which, when the image forming apparatus is turned on, outputs a disable signal to disable the access to the CPU, and, when at least the decryption and authentication of the decrypted data is completed, outputs an enable signal to enable the access to the CPU.

29. The image forming apparatus as claimed in claim 28, wherein the first circuit comprises a first register,

wherein, when the at least the decryption and authentication of the decrypted data is completed, the CPU changes a storage value of the first register.

30. The image forming apparatus as claimed in claim 25, wherein, when at least the decryption and authentication of the decrypted data is completed, the CPU performs a register setting job to disable access to the first memory and change the access to the first memory to access to the second memory.

31. The image forming apparatus as claimed in claim 25, wherein, when the image forming apparatus is turned on, the CPU identifies a memory that is designated by a setting value stored in the third memory or an external pin, and when the first memory is designated, the CPU performs secure boot using the encrypted data, and, when the second memory is designated, the CPU performs normal boot using non-encrypted data which is stored in the external non-volatile memory.

32. The image forming apparatus as claimed in claim 25, wherein the first memory is a mask Read Only Memory (ROM) or an one-time programmable (OTP) ROM,

wherein the second memory is a static random access memory (SRAM),

wherein the third memory is an electrical fuse (EFUSE) memory.

33. The image forming apparatus as claimed in claim 24, wherein the non volatile memory comprises a plurality of pins, wherein a writing pin to receive a writing signal output from the system on chip from among the plurality of pins is inactivated.

34. The image forming apparatus as claimed in claim 33, wherein the system on chip and the non volatile memory are embedded in a main board, wherein the writing pin is tied to an inactivated terminal on the main board.

35. The image forming apparatus as claimed in claim 24, wherein the system on chip further comprises a memory controller configured to control access to the external non volatile memory,

wherein the memory controller, when a writing signal on the external non volatile memory and a first key value are transmitted from the CPU, compares the first key value with a pre-stored second key value, and when the values are the same with each other, performs a writing operation on the external non volatile memory according to the writing signal.

36. The image forming apparatus as claimed in claim 35, wherein the memory controller comprises:

a signal transferring unit to store the first key value transmitted from the CPU;

a key value storage to store the second key value;

a comparing unit to compare the first key value stored in the signal transferring unit with the second key value stored in the key value storage; and

a signal transceiver to output the writing signal transmitted from the CPU to the external non volatile memory according to the compared result.

37. A method of booting of an image forming apparatus comprising a non-volatile memory and a system on chip, the method comprising:

initializing the image forming apparatus using initialization data which is stored in a first memory of the system on chip;

when the initializing is performed, decrypting encrypted data which is stored in the non-volatile memory using one of a plurality of encryption keys which are stored in the first memory;

storing the decrypted data in a second memory of the system on chip; and

performing a boot operation using data which is stored in the second memory.

38. The method as claimed in claim 37, further comprising:

when the image forming apparatus is turned on, identifying a memory that is designated according to an input value input through a third memory of the system on chip or an external pin; and

when the designated memory is the first memory, disabling access to a CPU of the system on chip.

39. The method as claimed in claim 38, further comprising, when at least the decryption and authentication of the decrypted data is completed, enabling the access to the CPU.

40. The method as claimed in claim 39, further comprising:

when the system preparation is completed, disabling the access to the first memory; and

performing register setting to change the access to the first memory to access to the second memory.

41. A host device comprising:

a storage to store a plurality of cipher texts corresponding to each of a plurality of versions;

a communication unit to receive a cipher text stored in an image forming apparatus when a predetermined event occurs;

a controller to control the image forming apparatus to be in a waiting state for printing when a cipher text corresponding to the firmware version of the image forming apparatus is the same as the received cipher text, and when the cipher text and the firmware version are different from each other, the controller blocks the use of the image forming apparatus.

42. An electronic device comprising:

a memory device; and

a system on chip including;

a central processing unit (CPU); and

a memory controller communicatively coupled to the CPU and the memory device, the memory controller to selectively output a writing signal received from the CPU to the memory device according to a result of a comparison between a first key value and a second key value.

43. The electronic device of claim 42, wherein the memory controller controls at least one switch to select a connection state so as to output the writing signal to the memory device when the first key value and the second key value are the same.

44. The electronic device of claim 43, wherein the memory controller controls the at least one switch so as to disable the connection to the memory device so as to prevent the writing signal from being output to the memory device.

45. The electronic device of claim 44, wherein the memory controller controls a read operation of the memory device even when the memory controller is preventing the writing signal from being output to the memory device.