SYSTEM AND METHODS FOR DYNAMIC MANAGEMENT OF HARDWARE RESOURCES

• US 20140165021A1
• Filed: 11/01/2013
• Published: 06/12/2014
• Est. Priority Date: 11/01/2012
• Status: Active Grant

• Current Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Original Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Inventors: Pattichis, Marios Stephanou, Jiang, Yuebing, Llamocca Obregon, Daniel Rolando
• Granted Patent: US 9,111,059 B2
• Time in Patent Office: Days
• US Class Current: 716/133
• CPC Class Codes: G06F 2111/06 Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: H03H 17/0241 Distributed arithmetic
• CPC Class Codes: H03H 17/0294 Variable filters; Programmable filters
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H04N 19/625 using discrete cosine transform [DCT]

Abstract

A dynamically reconfigurable framework manages processing applications in order to meet time-varying constraints to select an optimal hardware architecture. The optimal architecture satisfies time-varying constraints including for example, supplied power, required performance, accuracy levels, available bandwidth, and quality of output such as image reconstruction. The process of determining an optimal solution is defined in terms of multi-objective optimization using Pareto-optimal realizations.

Claims

1. A field programmable gate array method for producing a dynamic reconfigurable framework for performing a task comprising the steps of:

varying one or more parameters to generate a space comprising a plurality of realizations, each realization defined by one or more selected from the group of;

a power value, an energy value, a performance value, a bitrate value, and an accuracy value;

determining the one or more realizations of the space that are optimal to obtain one or more optimal realizations, wherein the one or more optimal realizations are established using multi-objective optimization;

selecting the one or more optimal realizations that meet or exceed one or more time-varying constraints; and

implementing the one or more optimal realizations using one or more selected from the group comprising of;

a dynamic partial reconfiguration and a dynamic frequency control.

2. The field programmable gate array method for producing a dynamic reconfigurable framework for performing a task according to claim 1, wherein the one or more parameters include frequency of operation.

3. The field programmable gate array method for producing a dynamic reconfigurable framework for performing a task according to claim 1, wherein the one or more time-varying constraints are selected from the group consisting of:

a minimum power value, a minimum energy level, a maximum performance value, a maximum accuracy value, and a minimum bitrate level.

4. The field programmable gate array method for producing a dynamic reconfigurable framework for performing a task according to claim 1, wherein the dynamic reconfigurable framework is applied to a pixel processor architecture.

5. The field programmable gate array method for producing a dynamic reconfigurable framework for performing a task according to claim 1, wherein the dynamic reconfigurable framework is applied to a digital filtering architecture.

6. The field programmable gate array method for producing a dynamic reconfigurable framework for performing a task according to claim 5, wherein the digital filtering architecture is one-dimensional.

7. The field programmable gate array method for producing a dynamic reconfigurable framework for performing a task according to claim 5, wherein the digital filtering architecture is two-dimensional.

8. The field programmable gate array method for producing a dynamic reconfigurable framework for performing a task according to claim 5, wherein video compression is accomplished using the Discrete Cosine Transform (DCT) hardware core and a Quality Factor.

9. The field programmable gate array method for producing a dynamic reconfigurable framework for performing a task according to claim 4, wherein the one or more parameters of the pixel processor architecture is selected from the group consisting of:

a number of cores, a number of bits of an input pixel, a number of bits of an output pixel, and a frequency of operation.

10. The field programmable gate array method for producing a dynamic reconfigurable framework for performing a task according to claim 5, wherein the one or more parameters of the digital filtering architecture are selected from the group consisting of:

a number of coefficients and a coefficient value.

11. The field programmable gate array method for producing a dynamic reconfigurable framework for performing a task according to claim 1, wherein the multi-objective optimization uses a Pareto-front.

12. The field programmable gate array method for producing a dynamic reconfigurable framework for performing a task according to claim 11, wherein the one or more optimal realizations that meet or exceed one or more time-varying constraints is a Pareto-point selected on the Pareto-front.