Tuning Capacitance to Enhance FET Stack Voltage Withstand
First Claim
1. A method of fabricating a stacked RF switch that includes a multiplicity of series connected constituent transistors in a series string for which internal nodes are those between each pair of adjacent transistors, the method comprising a step of establishing total effective drain-source capacitance Cds values that are significantly different for different transistors in the stack, wherein:
- a) such difference is at least 2% between a maximum Cds value and a minimum Cds value of the constituent transistors of the stacks;
orb) for at least half of adjacent transistor pairs, a difference between Cds values of each pair differs by an amount greater than a total Cpd of an internal node between such pair, where the total Cpd of a node is a sum of all parasitic capacitance elements coupled to the node that are not part of a Cds.
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Accused Products
Abstract
An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.
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Citations
11 Claims
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1. A method of fabricating a stacked RF switch that includes a multiplicity of series connected constituent transistors in a series string for which internal nodes are those between each pair of adjacent transistors, the method comprising a step of establishing total effective drain-source capacitance Cds values that are significantly different for different transistors in the stack, wherein:
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a) such difference is at least 2% between a maximum Cds value and a minimum Cds value of the constituent transistors of the stacks;
orb) for at least half of adjacent transistor pairs, a difference between Cds values of each pair differs by an amount greater than a total Cpd of an internal node between such pair, where the total Cpd of a node is a sum of all parasitic capacitance elements coupled to the node that are not part of a Cds. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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- 9. A method of fabricating a stacked RF switch that includes a multiplicity of series connected constituent transistors in a series string for which internal nodes are those between each pair of adjacent transistors, the method comprising coupling a discrete capacitive feature to one or more internal nodes of the stack, where a discrete capacitive feature is a distinct element having an impedance that is predominantly capacitive at a primary frequency of a signal ordinarily switched by the RF switch.
Specification