ENCODED INFORMATION READING TERMINAL WITH MULTIPLE IMAGING ASSEMBLIES

• US 20140166755A1
• Filed: 09/20/2013
• Published: 06/19/2014
• Est. Priority Date: 09/27/2012
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Liu, Yong, Wang, Ynjiun Paul, Tao, Xi
• Granted Patent: US 9,342,723 B2
• Time in Patent Office: Days
• US Class Current: 235/440
• CPC Class Codes: G06K 7/10722 Photodetector array or CCD scanning

Abstract

An encoded information reading (EIR) terminal can comprise a microprocessor, a communication interface, an image processing circuit communicatively coupled to the microprocessor, a plurality of imaging assemblies communicatively coupled to the image processing circuit, and one or more memory blocks communicatively coupled to the image processing circuit. Each imaging assembly of the plurality of imaging assemblies can be configured to output image frame data. The image processing circuit can be configured to receive the image frame data from at least one imaging assembly, buffer the image frame data received from at least one imaging assembly in at least one memory block, and/or process the image frame data received from at least one imaging assembly. The EIR terminal can be configured to output image frame data comprising decodable indicia and/or decoded message data corresponding to the decodable indicia.

Claims

1. An encoded information reading (EIR) terminal comprising:

a microprocessor;

a communication interface;

an image processing circuit communicatively coupled to said microprocessor;

a plurality of imaging assemblies communicatively coupled to said image processing circuit;

one or more memory blocks communicatively coupled to said image processing circuit;

wherein each imaging assembly of said plurality of imaging assemblies is configured to output image frame data;

wherein said image processing circuit is configured to perform at least one of;

receiving said image frame data from at least one imaging assembly of said plurality of imaging assemblies, buffering said image frame data received from at least one imaging assembly of said plurality of imaging assemblies in at least one memory block of said one or more memory blocks, and processing said image frame data received from at least one imaging assembly of said plurality of imaging assemblies; and

wherein said EIR terminal is configured to output at least one of;

image frame data comprising decodable indicia and decoded message data corresponding to said decodable indicia.

2. The EIR terminal of claim 1, wherein each imaging assembly of said plurality of imaging assemblies comprises a two-dimensional image sensor configured to output an analog signal representative of light reflected by an object located within a field of view of said imaging assembly, an amplifier configured to output an amplified analog signal by amplifying an analog signal read out of said image sensor, and an analog-to-digital (A/D) converter configured to convert said analog signal into a digital signal representing said image frame data.

3. The EIR terminal of claim 1, wherein said image processing circuit is configured to simultaneously communicate with at least two imaging assemblies of said plurality of imaging assemblies.

4. The EIR terminal of claim 1, wherein said image processing circuit is configured to simultaneously communicate with at least two memory blocks of said one or more memory blocks.

5. The EIR terminal of claim 1, wherein at least one imaging assembly of said plurality of imaging assemblies is communicatively coupled to said image processing circuit via one of:

a parallel interface, a serial interface.

6. The EIR terminal of claim 1, wherein at least one imaging assembly of said plurality of imaging assemblies includes a monochrome image sensor.

7. The EIR terminal of claim 1, wherein at least one imaging assembly of said plurality of imaging assemblies includes a color image sensor.

8. The EIR terminal of claim 1, wherein said processing of said image frame data received from at least one imaging assembly comprises at least one of:

filtering said image frame data, extracting a part of said image frame data.

9. The EIR terminal of claim 1, wherein said image processing circuit is provided by one of:

a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC).

10. The EIR terminal of claim 1, wherein said image processing circuit is configured to receive at least one image processing command from said microprocessor.

11. The EIR terminal of claim 1, wherein said image processing circuit is communicatively coupled to said microprocessor via at least one of:

a memory, a memory-like interface.

12. The EIR terminal of claim 1, wherein said communication interface is provided by one of:

a wired communication interface, a wireless communication interface.

13. An encoded information reading (EIR) terminal comprising:

a microprocessor;

a communication interface;

an image processing circuit communicatively coupled to said microprocessor;

a plurality of imaging assemblies of communicatively coupled to said image processing circuit via a standardized interface;

wherein each imaging assembly of said plurality of imaging assemblies is configured to output image frame data in a common format required by said standardized interface;

wherein each imaging assembly of said plurality of imaging assemblies comprises a two-dimensional image sensor configured to output an analog signal representative of light reflected by an object located within a field of view of said imaging assembly;

wherein said image processing circuit is configured to receive said image frame data from at least one imaging assembly of said plurality of imaging assemblies; and

wherein said EIR terminal is configured to output at least one of;

image frame data comprising decodable indicia and decoded message data corresponding to said decodable indicia.

14. The EIR terminal of claim 13, wherein said standardized interface is provided by one of:

a parallel interface, a serial interface.

15. The EIR terminal of claim 13, wherein said standardized interface is provided by one of:

a MIPI camera parallel interface, a MIPI camera serial interface.

16. The EIR terminal of claim 13, wherein said image processing circuit is configured to simultaneously communicate with at least two imaging assemblies of said plurality of imaging assemblies.

17. The EIR terminal of claim 13, wherein said image processing circuit is configured to receive at least one image processing command from said microprocessor.

18. The EIR terminal of claim 13, further comprising one or more memory blocks communicatively coupled to said image processing circuit.

19. The EIR terminal of claim 18, wherein said image processing circuit is further configured to perform at least one of:

buffering said image frame data received from at least one imaging assembly of said plurality of imaging assemblies in at least one memory block of said one or more memory blocks and processing said image frame data received from at least one imaging assembly of said plurality of imaging assemblies.

20. The EIR terminal of claim 18, wherein said image processing circuit is configured to simultaneously communicate with at least two memory blocks of said one or more memory blocks.