VERTICAL NANOWIRE TRANSISTOR WITH AXIALLY ENGINEERED SEMICONDUCTOR AND GATE METALLIZATION
First Claim
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1. A vertical nanowire transistor having a longitudinal axis perpendicularly oriented to a surface plane of a crystalline substrate, the transistor comprising:
- a group IV or group III-V epitaxial source semiconductor layer vertically aligned with an epitaxial group IV or group III-V drain semiconductor layer along the longitudinal axis;
a group IV or group III-V epitaxial channel semiconductor layer disposed between source and drain semiconductor layers, the channel semiconductor layer having an epitaxial film thickness associated with a channel length of the transistor; and
an annular gate electrode surrounding a sidewall of the semiconductor channel layer, separated by an annular gate dielectric layer, and wherein the composition of at least one of the gate electrode or the semiconductor layers varies along the longitudinal axis.
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Abstract
Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.
66 Citations
22 Claims
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1. A vertical nanowire transistor having a longitudinal axis perpendicularly oriented to a surface plane of a crystalline substrate, the transistor comprising:
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a group IV or group III-V epitaxial source semiconductor layer vertically aligned with an epitaxial group IV or group III-V drain semiconductor layer along the longitudinal axis; a group IV or group III-V epitaxial channel semiconductor layer disposed between source and drain semiconductor layers, the channel semiconductor layer having an epitaxial film thickness associated with a channel length of the transistor; and an annular gate electrode surrounding a sidewall of the semiconductor channel layer, separated by an annular gate dielectric layer, and wherein the composition of at least one of the gate electrode or the semiconductor layers varies along the longitudinal axis. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of fabricating a vertical nanowire transistor having a longitudinal axis perpendicularly oriented to a surface plane of a crystalline substrate, the method comprising:
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growing a plurality of crystalline semiconductor layers epitaxially from the substrate, the plurality including at least; a group IV or group III-V source semiconductor layer; a group IV or group III-V drain semiconductor layer; and a group IV or group III-V channel semiconductor layer disposed between source and drain semiconductor layers, wherein the epitaxial growing further comprises modifying growth conditions to vary the semiconductor composition across a thickness of the channel semiconductor layer; etching through at least the channel semiconductor layer to form a sidewall through the channel semiconductor layer; and forming a gate dielectric layer and a gate electrode on the channel semiconductor layer sidewall. - View Dependent Claims (16, 17, 18, 19)
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20. A method of fabricating a vertical nanowire transistor having a longitudinal axis perpendicularly oriented to a surface plane of a crystalline substrate, the method comprising:
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growing a plurality of crystalline semiconductor layers epitaxially from the substrate, the plurality including at least; a group IV or group III-V source semiconductor layer; a group IV or group III-V drain semiconductor layer; and a group IV or group III-V channel semiconductor layer disposed between source and drain semiconductor layers; etching through at least the channel semiconductor layer to form a sidewall through the channel semiconductor layer; and forming a gate dielectric layer and a gate electrode on the channel semiconductor layer sidewall, wherein forming the gate electrode further comprises modifying deposition conditions to vary the gate electrode composition across a thickness of the channel semiconductor layer. - View Dependent Claims (21, 22)
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Specification