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VERTICAL NANOWIRE TRANSISTOR WITH AXIALLY ENGINEERED SEMICONDUCTOR AND GATE METALLIZATION

  • US 20140166981A1
  • Filed: 12/18/2012
  • Published: 06/19/2014
  • Est. Priority Date: 12/18/2012
  • Status: Active Grant
First Claim
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1. A vertical nanowire transistor having a longitudinal axis perpendicularly oriented to a surface plane of a crystalline substrate, the transistor comprising:

  • a group IV or group III-V epitaxial source semiconductor layer vertically aligned with an epitaxial group IV or group III-V drain semiconductor layer along the longitudinal axis;

    a group IV or group III-V epitaxial channel semiconductor layer disposed between source and drain semiconductor layers, the channel semiconductor layer having an epitaxial film thickness associated with a channel length of the transistor; and

    an annular gate electrode surrounding a sidewall of the semiconductor channel layer, separated by an annular gate dielectric layer, and wherein the composition of at least one of the gate electrode or the semiconductor layers varies along the longitudinal axis.

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