System and Method for Critical Path Replication

• US 20140167812A1
• Filed: 12/14/2012
• Published: 06/19/2014
• Est. Priority Date: 12/14/2012
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Inventors: Jain, Abhishek, Chatterjee, Kallol, Parthasarathy, Chittoor
• Granted Patent: US 9,160,336 B2
• Time in Patent Office: Days
• US Class Current: 326/16
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: H03K 19/003 Modifications for increasing the reliability for protection
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

Disclosed is a system and method for providing a critical path replica system in a circuit. A critical path replica system is created by determining a critical path in a circuit, generating a critical path replica circuit, generating a circuit blueprint, and creating the blueprinted circuit. The circuit comprises a functional logic module having functional logic elements and replica logic modules having logic elements. Each logic element is configured to replicate one or more of the functional logic elements and process a test signal. A replica error detection module analyzes the processed signal to determine whether a timing violation has occurred. In some embodiments, the replica logic module further comprises one or more load modules. A replica controller may modify operation of the circuit based on reported errors. A replica mode select module sets the replica logic module to an aging test mode or a timing sensor mode.

Claims

1. A circuit comprising:

at least one functional logic module having at least one functional logic element;

a replica data control module configured to provide a test signal;

at least one replica logic module comprising logic elements, each of the logic elements configured to replicate one or more of the functional logic elements, the logic elements configured to process the test signal and generate a processed signal; and

a replica error detection module configured to analyze the processed signal to determine whether a timing violation has occurred in the replica logic module.

2. The circuit of claim 1, further comprising:

a replica mode control module configured set the replica logic module to an aging test mode and a timing sensor mode.

3. The circuit of claim 2, further comprising a data bus configured to provide data to the functional logic module, and wherein the replica mode control module is configured to set the replica logic module to the aging test mode by providing data from the data bus to the replica logic module.

4. The circuit of claim 2, wherein the replica mode control module is configured to set the replica logic module to the timing sensor mode by providing a predetermined data configuration to the replica logic module.

5. The circuit of claim 1, wherein the replica error detection module is configured to analyze the processed signal by comparing the processed signal to a reference signal.

6. The circuit of claim 1, wherein the critical path replica spatially replicates the functional logic module and is disposed within a predetermined distance from the critical path sufficient to bring the critical path replica within a desired process variation window.

7. The circuit of claim 1, the replica logic module further comprising one or more load modules, each load module associated with a logic element and applying a load to an output of the associated logic element.

8. A circuit comprising:

a replica data control module configured to provide a test signal;

at least one replica logic module comprising at least one logic element, each logic element configured to replicate one or more functional logic elements in the circuit, the at least one logic element configured to process the test signal and generate a processed signal;

a replica error detection module configured to analyze the processed signal and generate an error report; and

a replica mode control module configured set the replica logic module to at least an aging test mode and a timing sensor mode.

9. The circuit of claim 8, further comprising a replica controller configured to modify operation of the circuit based on the error report.

10. The circuit of claim 9, further comprising at least one dedicated timing replica logic module configured to replicate the one or more functional logic elements in the circuit and having a delay margin control module disposed therein, and wherein the replica controller is further configured to receive an output from the dedicated timing replica logic module and from the replica logic module, and further configured to control the delay margin control module in the dedicated timing replica logic.

11. The circuit of claim 8, further comprising a data bus wherein the replica mode control module is configured to set the replica logic module to the aging test mode and provide data from the data bus to the replica logic module, the data from the data bus being substantially the same data provided to the functional logic element being replicated by a logic element.

12. The circuit of claim 8, further comprising a data bus configured to provide data to the functional logic elements in the circuit, and wherein the replica mode control module is configured to set the replica logic module to the timing sensor mode and provide a data configuration to the replica logic module to create an inverter configuration in the replica logic module.

13. The circuit of claim 8, wherein the replica error detection module comprises an error analysis module configured to compare a processed signal to a reference signal and generate an error signal when the processed signal and reference signal fail to match.

14. A method for creating a critical path replica system, comprising:

determining a critical path in a circuit for replication from an initial netlist;

determining critical path cells;

generating an updated netlist having critical path replica circuit elements;

generating a critical path replica circuit;

generating a circuit blueprint representing a circuit having the critical path and the critical path replica circuit; and

creating a circuit based on the circuit blueprint.

15. The method of claim 14, further comprising replicating the critical path to generate the critical path replica circuit.

16. The method of claim 15, wherein replicating the critical path comprises duplicating elements of the critical path in the critical path replica circuit.

17. The method of claim 15, wherein the circuit blueprint is generated by placing and routing the elements and connections of the circuit and the critical path replica.

18. The method of claim 17, wherein the critical path and the critical path replica circuit are placed in a same region of the circuit.

19. The method of claim 14, wherein the circuit blueprint is iteratively analyzed and modified until parameters of the circuit having the critical path and critical path replica circuit represented by the circuit blueprint fall within predetermined guidelines.

20. The method of claim 14, further comprising determining loads for critical path elements and generating one or more load modules in the netlist.