LINEAR RESISTOR WITH HIGH RESOLUTION AND BANDWIDTH
First Claim
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1. An apparatus comprising:
- a first voltage follower;
a second voltage follower; and
a pass-gate including a p-type transistor in parallel to an n-type transistor, wherein gate terminal of the p-type transistor is controlled by an output of the first voltage follower, and wherein gate terminal of the n-type transistor is controlled by an output of the second voltage follower.
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Abstract
Described is an apparatus which comprises: a first voltage follower; a second voltage follower; and a pass-gate including a p-type transistor in parallel to an n-type transistor, wherein gate terminal of the p-type transistor is controlled by an output of the first voltage follower, and wherein gate terminal of the n-type transistor is controlled by an output of the second voltage follower.
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Citations
20 Claims
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1. An apparatus comprising:
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a first voltage follower; a second voltage follower; and a pass-gate including a p-type transistor in parallel to an n-type transistor, wherein gate terminal of the p-type transistor is controlled by an output of the first voltage follower, and wherein gate terminal of the n-type transistor is controlled by an output of the second voltage follower. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 19, 20)
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13. An apparatus comprising:
a Continuous-Time Linear Equalizer (CTLE) with programmable linear resistor, the programmable linear resistor comprising; a first input; a second input; a first voltage follower; a second voltage follower; and a pass-gate including a p-type transistor in parallel to an n-type transistor, wherein gate terminal of the p-type transistor is controlled by an output of the first voltage follower, wherein gate terminal of the n-type transistor is controlled by an output of the second voltage follower, and wherein the first and second inputs are coupled to either non-gate terminals of the pass-gate. - View Dependent Claims (14, 15, 16)
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17. A system comprising:
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a memory unit; a processor, coupled to the memory unit, the processor including an receiver with a programmable resistor comprising; a first voltage follower; a second voltage follower; and a pass-gate including a p-type transistor in parallel to an n-type transistor, wherein gate terminal of the p-type transistor is controlled by an output of the first voltage follower, and wherein gate terminal of the n-type transistor is controlled by an output of the second voltage follower; and a wireless interface for allowing the processor to communicate with another device. - View Dependent Claims (18)
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Specification