Antenna Apparatus and Method

• US 20140168014A1
• Filed: 12/13/2012
• Published: 06/19/2014
• Est. Priority Date: 12/13/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Monsen, Yeh, En-Hsiang, Wang, Chuei-Tang, Yu, Chen-Hua, Chih, Lai Wei
• Granted Patent: US 9,431,369 B2
• Time in Patent Office: Days
• US Class Current: 343/700.MS
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 1/36 : Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewithH01Q1/08, H01Q1/14 take precedence
• CPC Class Codes: H01Q 9/0407 : Substantially flat resonant element parallel to ground plane, e.g. patch antenna dipole H01Q9/285; monopole H01Q9/40

Abstract

An antenna apparatus comprises a semiconductor die comprising a plurality of active circuits, a molding layer formed over the semiconductor die, wherein the semiconductor die and the molding layer form a fan-out package, a first dielectric layer formed on a first side of the semiconductor die over the molding compound layer, a first redistribution layer formed in the first dielectric layer and an antenna structure formed above the semiconductor die and coupled to the plurality of active circuits through the first redistribution layer.

Claims

1. A device comprising:

a semiconductor die embedded in a molding compound layer;

a plurality of post passivation interconnects formed over the molding compound layer; and

an antenna structure electrically connected to the semiconductor die through the plurality of post passivation interconnects, wherein the antenna structure is formed by an interconnect of the semiconductor die.

2. The device of claim 1, wherein:

the plurality of post passivation interconnects are formed over a first side of the semiconductor die; and

the antenna structure is formed above a second side of the semiconductor die, wherein the antenna structure is electrically connected to the plurality of post passivation interconnects through a through via.

3. The device of claim 2, wherein:

the through via is formed in the molding compound layer.

4. The device of claim 2, wherein:

the through via is formed in the semiconductor die.

5. The device of claim 1, wherein:

the plurality of post passivation interconnects are formed over a first side of the semiconductor die; and

the antenna structure is formed above the first side of the semiconductor die, wherein the antenna structure is electrically connected to the plurality of post passivation interconnects through an interconnect structure.

6. The device of claim 5, further comprising:

a plurality of metal bumps formed above a second side of the semiconductor die; and

a first interconnect structure formed over the first side of the semiconductor die, wherein the antenna structure is electrically connected to the semiconductor die through the first interconnect structure.

7. The device of claim 6, wherein:

the first interconnect structure and the plurality of post passivation interconnects are configured such that;

a variety of active circuits in the semiconductor die are electrically connected to the antenna structure through connection paths formed by the first interconnect structure and the plurality of post passivation interconnects.

8. A device comprising:

a semiconductor die comprising a plurality of active circuits;

a molding compound layer formed over the semiconductor die, wherein the semiconductor die and the molding compound layer form a fan-out package;

a first dielectric layer formed on a first side of the semiconductor die over the molding compound layer;

a first interconnect structure formed in the first dielectric layer; and

an antenna structure formed above the semiconductor die and electrically connected to the plurality of active circuits through the first interconnect structure, wherein the antenna structure is formed by an interconnect.

9. The device of claim 8, further comprising:

a second dielectric layer formed on the first dielectric layer over the molding compound layer; and

a post passivation interconnect formed in the second dielectric layer, wherein the antenna structure is electrically connected to the plurality of active circuits through the post passivation interconnect.

10. The device of claim 8, further comprising:

a through via formed in the molding compound layer;

a second side dielectric layer formed on a second side of the semiconductor die over the molding compound layer; and

a metal bump formed over the second side dielectric layer.

11. The device of claim 10, wherein:

the through via, the first interconnect structure, the metal bump and the antenna structure are configured such that;

the plurality of active circuits in the semiconductor die are electrically connected to the antenna structure and the metal bump through connection paths formed by the through via, the first interconnect structure and a plurality of post passivation interconnects.

12. The device of claim 10, wherein:

the first interconnect structure is an interconnect via.

13. The device of claim 8, wherein:

the antenna structure is formed of copper.

14. The device of claim 8, wherein:

the antenna structure is of a meander line shape.

15. A method comprising:

embedding a semiconductor die in a molding compound layer;

forming a first group of through vias in the molding compound layer;

forming a first interconnect structure on a first side of the semiconductor die, wherein the first interconnect structure is coupled the semiconductor die through the first group of through vias;

depositing a first dielectric layer over the molding compound layer, wherein the first interconnect structure is embedded in the first dielectric layer;

forming a post passivation interconnect over the first dielectric layer; and

formed an antenna structure above the post passivation interconnect, wherein the antenna structure is electrically connected to the semiconductor die.

16. The method of claim 15, further comprising:

attaching the semiconductor die on a first carrier;

forming a first side structure above the semiconductor die;

detaching the first carrier from the semiconductor die;

flipping the semiconductor die;

attaching the semiconductor die on a second carrier;

forming a second side structure above the semiconductor die; and

detaching the second carrier from the semiconductor die.

17. The method of claim 15, further comprising:

coupling the antenna structure with the semiconductor die by using a through via, the first interconnect structure, wherein the through via is formed in the molding layer.

18. The method of claim 15, further comprising:

coupling the antenna structure with the semiconductor die by using a through via, the first interconnect structure, wherein the through via is formed in the semiconductor die.

19. The method of claim 15, further comprising:

coupling the antenna structure with the semiconductor die through the post passivation interconnect and the first interconnect structure.

20. The method of claim 15, further comprising:

depositing a second side dielectric layer on a second side of the semiconductor die over the molding compound layer; and

forming a metal bump over the second side dielectric layer.