POWER MANAGEMENT SRAM WRITE BIT LINE DRIVE CIRCUIT

• US 20140169076A1
• Filed: 12/18/2012
• Published: 06/19/2014
• Est. Priority Date: 12/18/2012
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Behrends, Derick G., Christensen, Todd A., Hebig, Travis R., Launsbach, Michael
• Granted Patent: US 9,058,861 B2
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A static random access memory (SRAM) having two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC) is disclosed. The SRAM may include a write driver logic coupled to the WBL and the WBLC. The write driver logic is adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel. The write driver logic is further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, where the downlevel is a second supply voltage lower than the first supply voltage.

Claims

1. A static random access memory (SRAM) comprising:

two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC);

a write driver logic coupled to the WBL and the WBLC, the write driver logic adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel;

the write driver logic further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, wherein the downlevel is a voltage suitable to be interpreted as a downlevel on the WBLC by two or more SRAM cells.

2. The SRAM of claim 1, wherein the write driver logic includes a first PFET transistor with a source connected to the supply voltage, a drain connected to the WBL, and a gate coupled with a first feedback path to turn off the first PFET transistor when the WBL reaches the uplevel, and a second PFET transistor with a source connected to the supply voltage, a drain connected to the WBLC, and a gate coupled with a second feedback path to turn off the second PFET transistor when the WBLC reaches the uplevel.

3. The SRAM of claim 2, wherein the first and second feedback paths are timed to turn off the first and second PFETs, respectively, so that the WBL and WBLC reach the uplevel.

4. The SRAM of claim 2, wherein the write driver logic includes a first NFET transistor with a source connected to ground, a drain connected to the WBL, and a gate coupled with a complement of a data input, and a second NFET transistor with a source connected to ground, a drain connected to the WBLC, and a gate coupled with the data input.

5. The SRAM of claim 2, wherein a first keeper device is connected between the WBL and the first supply voltage and a second keeper device is connected between the WBLC and the first supply voltage, to maintain the selected bit line at the uplevel.

6. The SRAM of claim 5, wherein the first keeper device includes a first keeper feedback path to maintain the WBL at the uplevel voltage until the WBL is driven to the downlevel voltage, and a second keeper device which includes a second keeper feedback path to maintain the WBLC at the uplevel voltage until the WBLC is driven to the downlevel voltage.

7. The SRAM of claim 6, wherein the first keeper feedback path comprises an NFET with a source coupled to the WBL and a drain coupled the first supply voltage, and the second keeper feedback path comprises an NFET with a source coupled to the WBLC and a drain coupled the first supply voltage.

8. A static random access memory (SRAM) comprising:

two or more SRAM memory cells connected with a write bit line (WBL);

a write driver logic coupled to the WBL;

the write driver logic adapted to drive the WBL to a voltage uplevel below a first supply voltage in response to a first logical value on a data input;

the write driver logic further adapted to shut off the drive to the WBL when the WBL reaches the uplevel;

the write driver logic further adapted to drive the WBL to a downlevel, in response to a second logical value on the data input, wherein the downlevel is a voltage suitable to be interpreted as a downlevel on the WBLC by two or more SRAM cells.

9. The SRAM of claim 8, wherein the write driver logic includes a PFET transistor with a source connected to the first supply voltage, a drain connected to the WBL, and a gate coupled with a feedback path to turn off the PFET transistor when the WBL reaches the uplevel.

10. The SRAM of claim 9, wherein the feedback path is timed to turn off the PFET so that the WBL voltage reaches the uplevel.

11. The SRAM of claim 9, wherein the write driver logic includes an NFET transistor with a source connected to ground, a drain connected to the WBL, and a gate coupled with a data input.

12. The SRAM of claim 9, wherein a keeper device is connected between the WBL and the first supply voltage to maintain WBL at the uplevel.

13. The SRAM of claim 12, wherein the keeper device includes a keeper feedback path to maintain the WBL at the uplevel voltage until the WBL is driven to the downlevel voltage.

14. The SRAM of claim 13, wherein the keeper feedback path comprises an NFET with a source coupled to the WBL and a drain coupled the first supply voltage.

15. A design structure tangibly embodied in a machine-readable storage medium used in a design process of an SRAM, the design structure having elements that, when processed in a semiconductor manufacturing facility, produce an SRAM that comprises:

two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC);

a write driver logic coupled to the WBL and the WBLC, the write driver logic adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel;

the write driver logic further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, wherein the downlevel is a second supply voltage lower than the first supply voltage.

16. The design structure of claim 15, wherein the design structure comprises a Netlist which describes the SRAM.

17. The design structure of claim 15, wherein the design structure resides on a storage medium as a data format used for the exchange of layout data of integrated circuits.

18. The design structure of claim 15, wherein the design structure includes at least one set of test data files, characterization data, verification data, or design specifications.

19. The design structure of claim 15, wherein the write driver logic includes a first PFET transistor with a source connected to the first supply voltage, a drain connected to the WBL, and a gate coupled with a first feedback path to turn off the first PFET transistor when the WBL reaches the uplevel, and a second PFET transistor with a source connected to the supply voltage, a drain connected to the WBLC, and a gate coupled with a second feedback path to turn off the second PFET transistor when the WBLC reaches the uplevel.

20. The design structure of claim 19, wherein the first and second feedback paths are timed to turn off the first and second PFETs, respectively, so that the WBL and WBLC voltage levels reach the uplevel.