LOW-DELAY BUFFERING MODEL IN VIDEO CODING

• US 20140169448A1
• Filed: 09/25/2013
• Published: 06/19/2014
• Est. Priority Date: 12/19/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Wang, Ye-Kui
• Granted Patent: US 9,374,585 B2
• Time in Patent Office: Days
• US Class Current: 375/240.02
• CPC Class Codes: H04N 19/115 Selection of the code volume for a coding unit prior to coding
• CPC Class Codes: H04N 19/146 Data rate or code amount at the encoder output
• CPC Class Codes: H04N 19/172 the region being a picture, frame or field
• CPC Class Codes: H04N 19/174 the region being a slice, e.g. a line of blocks or a group of blocks
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/433 characterised by techniques for memory access
• CPC Class Codes: H04N 19/70 characterised by syntax aspects related to video coding, e.g. related to compression standards

Abstract

Techniques for low-delay buffering in a video coding process are disclosed. Video decoding techniques may include receiving a first decoded picture buffer (DPB) output delay and a second DPB output delay for a decoded picture, determining, for the decoded picture, a first DPB output time using the first DPB output delay in the case a hypothetical reference decoder (HRD) setting for a video decoder indicates operation at a picture level, and determining, for the decoded picture, a second DPB output time using the second DPB output delay in the case that the HRD setting for the video decoder indicates operation at a sub-picture level.

Claims

1. A method of decoding video, the method comprising:

receiving a first decoded picture buffer (DPB) output delay and a second DPB output delay for a decoded picture;

determining, for the decoded picture, a first DPB output time using the first DPB output delay in the case a hypothetical reference decoder (HRD) setting for a video decoder indicates operation at a picture level; and

determining, for the decoded picture, a second DPB output time using the second DPB output delay in the case that the HRD setting for the video decoder indicates operation at a sub-picture level.

2. The method of claim 1, further comprising:

receiving a sub-picture coded picture buffer (CPB) flag that indicates whether the HRD setting for the video decoder is at the picture level or at the sub-picture level;

decoding video pictures based on the sub-picture CPB flag; and

outputting pictures from a decoded picture buffer based on the first DPB output time or the second DPB output time, wherein the first DPB output time is used if the sub-picture CPB flag indicates that the HRD setting for the video decoder indicates operation at the picture level, and wherein the second DPB output time is used if the sub-picture CPB flag indicates that the HRD setting for the video decoder indicates operation at the sub-picture level.

3. The method of claim 1, wherein determining the second DPB output time comprises multiplying the second DPB output delay by a sub-picture clock tick and adding a resultant value to a CPB removal time.

4. The method of claim 1, wherein determining the first DPB output time comprises multiplying the first DPB output delay by a clock tick and adding a resultant value to a CPB removal time.

5. A method of encoding video, the method comprising:

determining a first decoded picture buffer (DPB) output time using a first DPB output delay in the case a hypothetical reference decoder (HRD) setting for a video decoder indicates operation at a picture level;

determining a second DPB output time using a second DPB output delay in the case that the HRD setting for the video decoder indicates operation at a sub-picture level; and

signaling the first DPB output delay and the second DPB output delay.

6. The method of claim 5, further comprising:

signaling a sub-picture coded picture buffer (CPB) flag that indicates whether the HRD setting for the video decoder is at the picture level or at the sub-picture level; and

encoding video pictures based on the sub-picture CPB flag.

7. The method of claim 5, wherein determining the second DPB output time comprises multiplying the second DPB output delay by a sub-picture clock tick and adding a resultant value to a CPB removal time.

8. The method of claim 5, wherein determining the first DPB output time comprises multiplying the first DPB output delay by a clock tick and adding a resultant value to a CPB removal time.

9. An apparatus configured to decode video data, the apparatus comprising:

a video decoder configured to;

receive a first decoded picture buffer (DPB) output delay and a second DPB output delay for a decoded picture;

determine, for the decoded picture, a first DPB output time using the first DPB output delay in the case a hypothetical reference decoder (HRD) setting for a video decoder indicates operation at a picture level; and

determine, for the decoded picture, a second DPB output time using the second DPB output delay in the case that the HRD setting for the video decoder indicates operation at a sub-picture level.

10. The apparatus of claim 9, wherein the video decoder is further configured to:

receive a sub-picture coded picture buffer (CPB) flag that indicates whether the HRD setting for the video decoder is at the picture level or at the sub-picture level;

decode video pictures based on the sub-picture CPB flag; and

output pictures from a decoded picture buffer based on the first DPB output time or the second DPB output time, wherein the first DPB output time is used if the sub-picture CPB flag indicates that the HRD setting for the video decoder indicates operation at the picture level, and wherein the second DPB output time is used if the sub-picture CPB flag indicates that the HRD setting for the video decoder indicates operation at the sub-picture level.

11. The apparatus of claim 9, wherein the video decoder is configured to determine the second DPB output time by multiplying the second DPB output delay by a sub-picture clock tick and adding a resultant value to a CPB removal time.

12. The apparatus of claim 9, wherein the video decoder is configured to determine the first DPB output time by multiplying the first DPB output delay by a clock tick and adding a resultant value to a CPB removal time.

13. An apparatus configured to encode video data, the apparatus comprising:

a video encoder configured to;

determine a first decoded picture buffer (DPB) output time using a first DPB output delay in the case a hypothetical reference decoder (HRD) setting for a video decoder indicates operation at a picture level;

determine a second DPB output time using a second DPB output delay in the case that the HRD setting for the video decoder indicates operation at a sub-picture level; and

signal the first DPB output delay and the second DPB output delay.

14. The apparatus of claim 13, wherein the video encoder is further configured to:

signal a sub-picture coded picture buffer (CPB) flag that indicates whether the HRD setting for the video decoder is at the picture level or at the sub-picture level; and

encode video pictures based on the sub-picture CPB flag.

15. The apparatus of claim 13, wherein the video encoder is configured to determine the second DPB output time comprises by the second DPB output delay by a sub-picture clock tick and adding a resultant value to a CPB removal time.

16. The apparatus of claim 13, wherein the video encoder is configured to determine the first DPB output time by multiplying the first DPB output delay by a clock tick and adding a resultant value to a CPB removal time.

17. An apparatus configured to decode video data, the apparatus comprising:

means for receiving a first decoded picture buffer (DPB) output delay and a second DPB output delay for a decoded picture;

means for determining, for the decoded picture, a first DPB output time using the first DPB output delay in the case a hypothetical reference decoder (HRD) setting for a video decoder indicates operation at a picture level; and

means for determining, for the decoded picture, a second DPB output time using the second DPB output delay in the case that the HRD setting for the video decoder indicates operation at a sub-picture level.

18. The apparatus of claim 17, further comprising:

means for receiving a sub-picture coded picture buffer (CPB) flag that indicates whether the HRD setting for the video decoder is at the picture level or at the sub-picture level;

means for decoding video pictures based on the sub-picture CPB flag; and

means for outputting pictures from a decoded picture buffer based on the first DPB output time or the second DPB output time, wherein the first DPB output time is used if the sub-picture CPB flag indicates that the HRD setting for the video decoder indicates operation at the picture level, and wherein the second DPB output time is used if the sub-picture CPB flag indicates that the HRD setting for the video decoder indicates operation at the sub-picture level.

19. The apparatus of claim 17, wherein the means for determining the second DPB output time comprises means for multiplying the second DPB output delay by a sub-picture clock tick and adding a resultant value to a CPB removal time.

20. The apparatus of claim 17, wherein the means for determining the first DPB output time comprises means for multiplying the first DPB output delay by a clock tick and adding a resultant value to a CPB removal time.

21. An apparatus configured to encode video data, the apparatus comprising:

means for determining a first decoded picture buffer (DPB) output time using a first DPB output delay in the case a hypothetical reference decoder (HRD) setting for a video decoder indicates operation at a picture level;

means for determining a second DPB output time using a second DPB output delay in the case that the HRD setting for the video decoder indicates operation at a sub-picture level; and

means for signaling the first DPB output delay and the second DPB output delay.

22. The apparatus of claim 21, further comprising:

means for signaling a sub-picture coded picture buffer (CPB) flag that indicates whether the HRD setting for the video decoder is at the picture level or at the sub-picture level; and

means for encoding video pictures based on the sub-picture CPB flag.

23. The apparatus of claim 21, wherein the means for determining the second DPB output time comprises means for multiplying the second DPB output delay by a sub-picture clock tick and adding a resultant value to a CPB removal time.

24. The apparatus of claim 21, wherein the means for determining the first DPB output time comprises means for multiplying the first DPB output delay by a clock tick and adding a resultant value to a CPB removal time.

25. A computer-readable storage medium storing instructions that, when executed, causes one or more processors of a device configured to decode video data to:

receive a first decoded picture buffer (DPB) output delay and a second DPB output delay for a decoded picture;

determine, for the decoded picture, a first DPB output time using the first DPB output delay in the case a hypothetical reference decoder (HRD) setting for a video decoder indicates operation at a picture level; and

determine, for the decoded picture, a second DPB output time using the second DPB output delay in the case that the HRD setting for the video decoder indicates operation at a sub-picture level.

26. The computer-readable storage medium of claim 25, wherein the instructions further cause the one or more processors to:

receive a sub-picture coded picture buffer (CPB) flag that indicates whether the HRD setting for the video decoder is at the picture level or at the sub-picture level;

decode video pictures based on the sub-picture CPB flag; and

output pictures from a decoded picture buffer based on the first DPB output time or the second DPB output time, wherein the first DPB output time is used if the sub-picture CPB flag indicates that the HRD setting for the video decoder indicates operation at the picture level, and wherein the second DPB output time is used if the sub-picture CPB flag indicates that the HRD setting for the video decoder indicates operation at the sub-picture level.

27. The computer-readable storage medium of claim 25, wherein the instructions cause the one or more processors to determine the second DPB output time by multiplying the second DPB output delay by a sub-picture clock tick and adding a resultant value to a CPB removal time.

28. The computer-readable storage medium of claim 25, wherein the instructions cause the one or more processors to determine the first DPB output time by multiplying the first DPB output delay by a clock tick and adding a resultant value to a CPB removal time.

29. A computer-readable storage medium storing instructions that, when executed, causes one or more processors of a device configured to encode video data to:

determine a first decoded picture buffer (DPB) output time using a first DPB output delay in the case a hypothetical reference decoder (HRD) setting for a video decoder indicates operation at a picture level;

determine a second DPB output time using a second DPB output delay in the case that the HRD setting for the video decoder indicates operation at a sub-picture level; and

signal the first DPB output delay and the second DPB output delay.

30. The computer-readable storage medium of claim 29, wherein the instructions further cause the one or more processors to:

signal a sub-picture coded picture buffer (CPB) flag that indicates whether the HRD setting for the video decoder is at the picture level or at the sub-picture level; and

encode video pictures based on the sub-picture CPB flag.

31. The computer-readable storage medium of claim 29, wherein the instructions cause the one or more processors to determine the second DPB output time comprises by the second DPB output delay by a sub-picture clock tick and adding a resultant value to a CPB removal time.

32. The computer-readable storage medium of claim 29, wherein the instructions cause the one or more processors to determine the first DPB output time by multiplying the first DPB output delay by a clock tick and adding a resultant value to a CPB removal time.