MTJ STACK AND BOTTOM ELECTRODE PATTERNING PROCESS WITH ION BEAM ETCHING USING A SINGLE MASK

• US 20140170776A1
• Filed: 12/04/2013
• Published: 06/19/2014
• Est. Priority Date: 12/07/2012
• Status: Active Grant

• Current Assignee: Avalanche Technology Incorporated
• Original Assignee: Avalanche Technology Incorporated
• Inventors: Satoh, Kimihiro, Jung, Dong Ha, Zhang, Jing, Chen, Benjamin, Huai, Yiming, Ranjan, Rajiv Yadav, Zhou, Yuchen
• Granted Patent: US 9,166,154 B2
• Time in Patent Office: Days
• US Class Current: 438/3
• CPC Class Codes: H10N 50/01 Manufacture or treatment

Abstract

Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step.

Claims

1. A method of fabricating an array of memory cells on a wafer comprising:

depositing a stack of layers for the memory cells including top electrode layer, a set of layers for memory elements and a bottom electrode layer on the wafer;

executing a first etching process to remove unmasked areas of at least the top electrode layer using a mask that defines the array of memory cells; and

performing a second etching process using ion beam etching to remove exposed layers around the array of memory cells including the bottom electrode layer while rotating the wafer and to clean exposed sidewalls of the set of layers for the memory elements, and wherein at least a portion of the ion beam etching is performed at a selected ion beam incidence angle greater than zero degrees.

2. The method of claim 1 wherein the first etching process further comprises using reactive ion etching RIE and stopping etching prior to exposing a barrier layer in the set of layers for memory elements.

3. The method of claim 1 wherein the first etching process further comprises using reactive ion etching RIE and stopping etching after exposing the bottom electrode layer.

4. The method of claim 1 wherein the first etching process further comprises using magnetized inductively coupled plasma etching.

5. The method of claim 1 wherein the second etching process further comprises a first etching step that includes removing the bottom electrode layer with a first ion beam incident angle with a first etch rate, and a second step etching step that uses a second ion beam incident angle with a second etch rate selected to clean exposed sidewalls and wherein the first etch rate is higher than the second etch rate.

6. The method of claim 1 wherein the first etching process stops etching after exposing the bottom electrode layer and the method further comprises depositing dielectric material on the sidewalls of the set of layers for the memory elements after executing the first etching process and before performing the second etching process.

7. The method of claim 6 wherein the dielectric material is an oxygen free dielectric material.

8. The method of claim 1 wherein the selected ion beam incidence angle is selected to achieve a desired slope of sidewalls of the memory elements.

9. The method of claim 8 wherein the selected ion beam incidence angle is used to control a critical dimension of the memory elements.

10. The method of claim 1 wherein rotating the wafer further comprises repetitively varying a rotation speed to achieve differential etching of the set of layer for the memory element at selected angular positions.

11. The method of claim 10 wherein the rotation speed is lower at predetermined angular positions in a rotation cycle to differentially increase a rate of material removal by ion beam etching from the memory element sidewall at the predetermined angular positions.

12. The method of claim 10 wherein variations in the rotation speed correct for differential redeposition and etching rates between long and short axes of the memory cells.

13. The method of claim 10 wherein variation in the rotation speed modifies an aspect ratio of the memory cells.