METHOD FOR FORMING DUMMY GATE

• US 20140170842A1
• Filed: 12/17/2013
• Published: 06/19/2014
• Est. Priority Date: 12/18/2012
• Status: Active Grant

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: NORO, Motoki, LIN, Tai-Chuan, KAWADA, Shinji
• Granted Patent: US 8,946,030 B2
• Time in Patent Office: Days
• US Class Current: 438/585
• CPC Class Codes: H01J 37/32082 Radio frequency generated discharge H01J37/32357, H01J37/32366, H01J37/32394 and H01J37/32403 take precedence
• CPC Class Codes: H01J 37/32192 Microwave generated discharge H01J37/32357, H01J37/32366, H01J37/32394, H01J37/32403 take precedence
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclosed is a method of forming a dummy gate in manufacturing a field effect transistor. The method includes a first process of exposing a workpiece having a polycrystalline silicon layer to plasma of HBr gas, and a second process of further exposing the workpiece to the plasma of HBr gas after the first process. The first process includes etching the polycrystalline silicon layer to form a dummy semiconductor part having a pair of side surfaces from the polycrystalline silicon layer, and forming a protection film based on a by-product of etching on the pair of side surfaces in such a manner that the thickness of the protection film becomes smaller toward a lower end of the dummy semiconductor part.

Claims

1. A method of forming a dummy gate in manufacturing a field effect transistor, the method comprising:

a first process of exposing a workpiece having a polycrystalline silicon layer to plasma of HBr gas, the first process including etching the polycrystalline silicon layer to form a dummy semiconductor part having a pair of side surfaces from the polycrystalline silicon layer, and forming a protection film based on a by-product of etching on the pair of side surfaces in such a manner that the thickness of the protection film becomes smaller toward a lower end of the dummy semiconductor part; and

a second process of further exposing the workpiece to the plasma of HBr gas after the first process.

2. The dummy gate forming method according to claim 1, further comprising:

a third process of further exposing the workpiece to plasma of bromine gas or plasma of chlorine gas after the second process.

3. The dummy gate forming method according to claim 1, wherein the plasma is generated by microwave.

4. The dummy gate forming method according to claim 1, wherein the field effect transistor is a fin type field effect transistor,

the workpiece includes one or more fin type semiconductor parts,

the polycrystalline silicon layer is provided to cover the one or more fin type semiconductor parts, and

the dummy semiconductor part is formed to extend in a direction intersecting with the one or more fin type semiconductor parts.

5. The dummy gate forming method according to claim 1, wherein, in the first process, plasma of oxygen gas plasma is generated together with the plasma of HBr gas.