Block Memory Engine

• US 20140173203A1
• Filed: 12/18/2012
• Published: 06/19/2014
• Est. Priority Date: 12/18/2012
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Forsyth, Andrew T.
• Application Number:
  US13/717,981
• Publication Number:
  US 20140173203A1
• Time in Patent Office: Days
• US Class Current: 711/120
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In an embodiment, a processor is disclosed and includes a cache memory and a memory execution cluster coupled to the cache memory. The memory execution cluster includes a memory execution unit to execute instructions including non-block memory instructions, and block memory logic to execute one or more block memory operations. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a cache memory; and

a memory execution cluster coupled to the cache memory, the memory execution cluster comprising;

a memory execution unit to execute instructions including non-block memory instructions; and

block memory logic to execute one or more block memory operations.

2. The processor of claim 1, wherein the block memory logic is configured to autonomously perform initialization of a block of memory to a given value responsive to a first block memory operation.

3. The processor of claim 1, wherein the block memory logic is configured to autonomously copy contents of a first storage block to a second storage block responsive to a second block memory operation.

4. The processor of claim 1, wherein the block memory logic is configured to compare a first block of memory to a second block of memory to determine whether there is a difference in stored data between corresponding storage locations of the first block of memory and the second block of memory, responsive to a third block memory operation.

5. The processor of claim 1, wherein the block memory logic is configured to execute a find operation to determine whether a match exists between a supplied value and any stored data value in a first block of memory.

6. The processor of claim 1, wherein the block memory logic is configured to execute a block prefetch of a first block of memory from a system memory to the cache memory responsive to a block prefetch operation.

7. The processor of claim 1, wherein the block memory logic is configured to execute a block evict operation to push a first block of memory out of an initial cache memory to another cache memory responsive to a block evict operation.

8. The processor of claim 1, wherein the block memory logic is configured to execute a block evict operation to push a first block of memory out of an initial cache memory to a system memory responsive to a block evict operation.

9. The processor of claim 1, wherein the block memory logic is configured to receive for execution, each block memory operation corresponding to a respective user level block memory instruction.

10. The processor of claim 1, wherein a first block memory operation includes a read for ownership request that upon execution claims ownership of a first portion of the cache memory for a subsequent write instruction.

11. The processor of claim 1, wherein the block memory logic is to execute a first block memory operation in parallel with the memory execution unit while the memory execution unit executes a first non-block memory instruction.

12. The processor of claim 1, wherein the block memory logic is to prefetch a first data block as part of execution of a first block memory operation, wherein a block prefetch is a configured operation of the block memory logic.

13. A method comprising:

receiving a first block memory operation in a memory execution cluster of a processor;

detecting the first block memory operation; and

executing the first block memory operation using block memory logic within the memory execution cluster, wherein the block memory logic is to execute block memory operations and wherein non-block memory instructions are to be executed by one of one or more memory execution units within the memory execution cluster that are distinct from the block memory logic.

14. The method of claim 13, wherein the block memory operation is a block evict operation that upon execution is to push a first block of memory out of a first memory to a second memory.

15. The method of claim 13, further comprising executing the block memory operation while the one memory execution unit executes one or more non-block memory instructions in parallel.

16. A system comprising:

a dynamic random access memory (DRAM) to store data; and

a processor including a memory execution cluster coupled to the DRAM, the memory execution cluster comprising;

a memory execution unit to execute non-block memory instructions; and

block memory logic configured to execute a block memory operation on a memory block stored in the DRAM or stored in a cache memory of the processor responsive to a user level block memory instruction, wherein the block memory operation is executed independent of the memory execution unit.

17. The system of claim 16, wherein the block memory logic is to execute the block memory operation by a prefetch of the memory block from the DRAM to one of one or more cache memories.

18. The system of claim 16, wherein the block memory logic is to execute the block memory operation in parallel with execution of a non-block memory instruction by the memory execution unit.

19. The system of claim 16, wherein the memory execution unit is to execute an out-of-order non-block memory instruction while the block memory logic executes the block memory operation.

20. The system of claim 16, wherein the block memory operation is a block evict operation to push a block of memory out of a cache memory of the processor to the DRAM.