Power Gating A Portion Of A Cache Memory

• US 20140173207A1
• Filed: 12/14/2012
• Published: 06/19/2014
• Est. Priority Date: 12/14/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wang, Ren, Samih, Ahmad, Delano, Eric, Shah, Pinkesh J., Chishti, Zeshan A., Maciocco, Christian, Tai, Tsung-Yuan Charlie
• Granted Patent: US 9,183,144 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a plurality of tiles, each tile including a core and a tile cache hierarchy, the tile cache hierarchy including a first level cache and a second level cache, wherein each of the first level cache and the second level cache is physically private to the tile; and

a controller coupled to the plurality of tiles, the controller including a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a first tile and to cause the second level cache of the first tile to be independently power gated, based at least in part on the utilization information.

2. The processor of claim 1, wherein the cache power control logic is to independently power gate the second level cache while the core is in an active state.

3. The processor of claim 1, wherein the cache power control logic is to cause the second level cache to be power gated when a miss rate of the first level cache is less than a first threshold.

4. The processor of claim 1, wherein the cache power control logic is to cause the second level cache to be power gated while the core is in a low power state and a core of at least another of the plurality of tiles is in an active state.

5. The processor of claim 1, wherein the cache power control logic is to determine an energy break even value and to cause the second level cache to be power gated when an estimated idle duration for the core is greater than the energy break even value.

6. The processor of claim 5, wherein the cache power control logic is to calculate the energy break even value using static values and dynamic values associated with the processor.

7. The processor of claim 5, wherein the cache power control logic is to prevent the second level cache from being power gated when the estimated idle duration is greater than the energy break even value, based on quality of service (QoS) information associated with a workload being executed on the processor.

8. The processor of claim 1, wherein when the second level cache is power gated, the first level cache is to issue a read request to a system memory responsive to a miss in the first level cache.

9. The processor of claim 1, wherein at least a portion of information stored in the second level cache is to be flushed to a different second level cache of a different one of the plurality of tiles before the second level cache is power gated.

10. A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

determining an estimated idle duration for a core of a multicore processor, the core associated with a private cache hierarchy including a first level cache, a mid-level cache (MLC) and a last level cache (LLC);

determining a time value for a break even condition; and

power gating the LLC when the estimated idle duration is greater than the time value, while at least one other core of the multicore processor associated with another private cache hierarchy remains in an active state.

11. The machine-readable medium of claim 10, wherein the method further comprises:

receiving performance metric information from the private cache hierarchy; and

comparing the performance metric information to a threshold value.

12. The machine-readable medium of claim 11, wherein the method further comprises power gating the LLC based on the comparison of the performance metric information to the threshold value.

13. The machine-readable medium of claim 11, wherein the performance metric information comprises a miss rate of the MLC and power gating the LLC when the miss rate is less than the threshold value.

14. The machine-readable medium of claim 10, wherein the method further comprises determining the estimated idle duration based at least in part on an idle duration report received from a device coupled to the multicore processor.

15. The machine-readable medium of claim 10, wherein the method further comprises determining the time value for a first workload and storing the time value in a storage of the multicore processor.

16. The machine-readable medium of claim 15, wherein the method further comprises determining a second time value for a break even condition associated with a second workload, and using the second time value to determine whether to power gate the LLC during execution of the second workload on the multicore processor.

17. A system comprising:

a multicore processor having a plurality of tiles, each tile including a core and a tile cache hierarchy, the tile cache hierarchy including a first level cache, a mid-level cache (MLC) and a last level cache (LLC), wherein each of the first level cache, the MLC and the LLC are private to the tile, and a cache power control logic to receive performance metric information regarding the tile cache hierarchy of a first tile of the plurality of tiles and to cause the LLC of the first tile to be power gated based at least in part on the performance metric information, while the core, the first level cache and the MLC of the first tile remain in an active state; and

a dynamic random access memory (DRAM) coupled to the multicore processor.

18. The system of claim 17, wherein the cache power control logic is to cause the LLC to be power gated when a miss rate of the MLC is less than a first threshold.

19. The system of claim 17, wherein the cache power control logic is to determine an energy break even value and to cause the LLC to be power gated when the energy break even value is less than an estimated idle duration for the core of the first tile.

20. The system of claim 19, wherein the cache power control logic is to prevent the LLC from being power gated when the energy break even value is less than the estimated idle duration, based on quality of service (QoS) information associated with a workload being executed on the core of the first tile.