MEMORY SYSTEM AND SYSTEM ON CHIP INCLUDING THE SAME

• US 20140173228A1
• Filed: 11/05/2013
• Published: 06/19/2014
• Est. Priority Date: 12/18/2012
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Dong-Han, KONG, Jae-Sop
• Application Number:
  US14/072,208
• Publication Number:
  US 20140173228A1
• Time in Patent Office: Days
• US Class Current: 711/159
• CPC Class Codes: G06F 2205/126 Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag
• CPC Class Codes: G06F 5/12 Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations

Abstract

In one example embodiment, a memory system includes a hierarchical first-in first-out (FIFO) memory configured to store data, and a FIFO controller configured to control inputting and outputting of data to and from the FIFO memory, wherein the FIFO memory includes a first layer. The first layer includes a high-speed input FIFO memory configured to receive data from an external device and a high-speed output FIFO memory configured to output data to the external device. The FIFO memory further includes a second layer. The second layer includes a main FIFO memory configured to receive data from the high-speed input FIFO memory and output data to the high-speed output FIFO memory.

Claims

1. A memory system comprising:

a hierarchical first-in first-out (FIFO) memory configured to store data; and

a FIFO controller configured to control inputting and outputting of data to and from the FIFO memory,

wherein the FIFO memory comprises;

a first layer including,

a high-speed input FIFO memory configured to receive data from an external device, and

a high-speed output FIFO memory configured to output data to the external device, and

a second layer including,

a main FIFO memory configured to receive data from the high-speed input FIFO memory and output data to the high-speed output FIFO memory.

2. The memory system of claim 1, wherein the FIFO controller comprises an input FIFO manager configured to,

input data to the high-speed input FIFO memory,

output data stored in the high-speed input FIFO memory, and

input the output data to the main FIFO memory.

3. The memory system of claim 2, wherein the FIFO controller further comprises:

an output FIFO manager configured to output data to the external device, wherein the input FIFO manager,

outputs data stored in the high-speed input FIFO memory, and

transmits the output data to the output FIFO manager in response to a request from the output FIFO manager.

4. The memory system of claim 2, wherein the FIFO controller further comprises an output FIFO manager configured to output data to the external device, wherein the input FIFO manager immediately transmits data destined for the high-speed input FIFO memory to the output FIFO manager in response to a request from the output FIFO manager.

5. The memory system of claim 1, wherein the FIFO controller comprises an output FIFO manager configured to,

output data stored in the main FIFO memory,

input the output data to the high-speed output FIFO memory, and

output data from the high-speed output FIFO memory.

6. The memory system of claim 1, wherein the FIFO memory is further configured to provide a virtual write pointer and a virtual read pointer to the external device.

7. The memory system of claim 6, wherein the FIFO memory is further configured to provide a write pointer and a read pointer corresponding to each of the high-speed input FIFO memory, the high-speed output FIFO memory, and the main FIFO memory.

8. The memory system of claim 1, wherein a length of a storage unit of the main FIFO memory is n times a length of a storage unit of the high-speed input FIFO memory and a length of a storage unit of the high-speed output FIFO memory, and

n is a natural number greater than one.

9. The memory system of claim 1, wherein the number of storage units of the main FIFO memory is greater than the number of storage units of the high-speed input FIFO memory and the number of storage units of the high-speed output FIFO memory.

10. The memory system of claim 9, wherein the number of storage units of the high-speed input FIFO memory is greater than the number of storage units of the high-speed output FIFO memory.

11. The memory system of claim 1, wherein the high-speed input FIFO memory and the high-speed output FIFO memory operate at a first frequency, and

the main FIFO memory operates at a second frequency, the second frequency being different from the first frequency.

12. The memory system of claim 11, wherein the first frequency is higher than the second frequency.

13. A system on chip (SoC) comprising:

a first electronic system configured to transmit data;

a second electronic system configured to receive the data; and

the memory system of claim 1 configured to temporarily store the data between the first electronic system and the second electronic system.

14. A memory comprising:

a first layer, operating at a first frequency, configured to at least one of receive data from an external device and output data to the external device; and

a second layer, operating at a second frequency, configured to at least one of receive the data from the first layer and output the data to the first layer.

15. The memory of claim 14, wherein the first layer includes:

an input first-in first-out (FIFO) memory configured to receive the data from the external device, and

an output FIFO memory configured to output the data to the external device.

16. The memory of claim 14, wherein the second layer includes:

a main FIFO memory configured to at least one of receive the data from the input FIFO memory and output the data to the input FIFO memory.

17. A memory system comprising:

the memory of claim 14, wherein the first layer and the second layer form a hierarchical first-in first-out (FIFO) memory, and

a FIFO controller configured to control inputting the data to the FIFO memory and outputting the data from the FIFO memory.

18. The memory of claim 14, wherein the first frequency has a higher value compared to the second frequency.

19. The memory of claim 15, wherein the number of storage units of the input FIFO memory is greater than the number of storage units of the output FIFO memory.

20. The memory of claim 15, wherein a length of a storage unit of a main FIFO memory of the second layer is greater than a length of a storage unit of the input FIFO memory and a length of a storage unit of the output FIFO memory.