RETURN ADDRESS TRACKING MECHANISM

• US 20140173290A1
• Filed: 12/17/2012
• Published: 06/19/2014
• Est. Priority Date: 12/17/2012
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: KAPLAN, DAVID A.
• Application Number:
  US13/717,329
• Publication Number:
  US 20140173290A1
• Time in Patent Office: Days
• US Class Current: 713/189
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
• CPC Class Codes: G06F 21/72 in cryptographic circuits

Abstract

A processor, a method and a computer-readable storage medium for tracking a return address are provided. The processor comprises a hardware register and logic configured to receive a call instruction. The logic is further configured to, based on the call instruction, encrypt a return address, store the encrypted return address onto a first address in a stack and store the first address on the hardware register.

Claims

1. A processor comprising:

a hardware register;

logic that is configured to receive a call instruction and, based thereon, to;

encrypt a return address;

store the encrypted return address into a first address in a stack; and

store the first address in the hardware register.

2. The processor of claim 1, wherein the logic is further configured to store an invalid address in the register in response to a return instruction.

3. The processor of claim 1, wherein:

the logic is further configured to compare a second address in a load instruction with the first address stored in the register; and

when the first and second addresses match, the logic is configured to decrypt a value in memory at the matching address and return the value as a response to the load instruction.

4. The processor of claim 1, wherein:

the logic is further configured to determine whether a store-queue contains a store instruction associated with a second address of a load instruction;

the logic is further configured to determine whether a type of the store instruction matches a type of a load instruction;

wherein, when there is a match, the logic is further configured to forward a data associated with the store; and

wherein, when there is no match, the logic is further configured to block the load instruction until the store is committed to a memory.

5. The processor of claim 1, wherein, after receiving an interrupt, the logic is further configured to store a value of the register in the stack.

6. The processor of claim 5, wherein, after receiving a return from the interrupt, the logic is further configured to restore the value of the register.

7. The processor of claim 1, wherein the logic is further configured to:

before storing the first address in the hardware register, calculate a difference between a the first address and a prior value in the hardware register; and

store the difference in the stack.

8. The processor of claim 7, wherein the difference is stored in the upper bits of the memory location pointed to by the first address and the encrypted return address is stored in the lower bits of the memory location pointed to by the first address.

9. The processor of claim 7, wherein the logic is further configured to, in response to a return instruction:

calculate the prior value in the hardware register based on the difference; and

store the prior value in the hardware register.

10. A method comprising:

receiving, using circuitry within a processor, a call instruction,

encrypting, using the circuitry, a return address;

storing, using the circuitry, the encrypted return address into a first address in a stack; and

storing, using the circuitry, the first address in a register.

11. The method of claim 10, further comprising:

receiving a return instruction; and

storing an invalid address in the register.

12. The method of claim 10, further comprising:

receiving a load instruction including a second address;

determining whether the first address stored in the register and the second address match; and

when there is a match;

decrypting a value pointed to by the matching address; and

returning the value as a response to the load instruction.

13. The method of claim 10, further comprising:

determining a type of store instruction associated with a second address of a load instruction that is stored in a store-and-forward queue; and

when the type matches a type of load instruction, forwarding a data associated with the store instruction, or

when the type does not match the type of load instruction, blocking the load instruction until the store is committed to a memory.

14. The method of claim 10, further comprising:

receiving an interrupt; and

storing a value of the register in the stack.

15. The method of claim 14, further comprising:

receiving a return from the interrupt; and

restoring the value of the register.

16. The method of claim 10, further comprising:

before storing the first address in the register, calculating a difference between a the first address and a prior value in the register; and

storing the difference in the stack.

17. The method of claim 16, wherein the difference is stored in the upper bits of the memory location pointed to by the first address and the encrypted return address is stored in the lower bits of the memory location pointed to by the first address.

18. The method of claim 16, further comprising, in response to a return instruction:

calculating the prior value in the register based on the difference; and

storing the prior value in the register.

19. A computer-readable storage device having instructions stored thereon, execution of which by a processor cause the processor to perform operations, the operations comprising:

receiving a call instruction,

encrypting a return address;

storing the encrypted return address into a first address in a stack; and

storing the first address in a register.

20. The computer-readable storage device of claim 19, further comprising:

receiving a return instruction; and

storing an invalid address in the register.

21. The computer-readable storage device of claim 19, further comprising:

receiving a load instruction including a second address;

determining whether the first address stored in the register and the second address match; and

when there is a match;

decrypting a value pointed to by the matching address; and

returning the value as a response to the load instruction.

22. The computer-readable storage device of claim 19, further comprising:

determining a type of store instruction associated with a second address of a load instruction that is stored in a store-and-forward queue; and

when the type matches a type of load instruction, forwarding a data associated with the store instruction, or

when the type does not match the type of load instruction, blocking the load instruction until the store is committed to a memory.

23. The computer-readable storage device of claim 19, further comprising:

receiving an interrupt; and

storing a value of the register in the stack.

24. The computer-readable storage device of claim 23, further comprising:

receiving a return from the interrupt; and

restoring the value of the register.

25. The computer-readable storage device of claim 19, further comprising:

before storing the first address in the register, calculating a difference between a the first address and a prior value in the register; and

storing the difference in the stack.

26. The computer-readable storage device of claim 25, wherein the difference is stored in the upper bits of the memory location pointed to by the first address and the encrypted return address is stored in the lower bits of the memory location pointed to by the first address.

27. The computer-readable storage device of claim 25, further comprising, in response to a return instruction:

calculating the prior value in the register based on the difference; and

storing the prior value in the register.