POWER STATE SYNCHRONIZATION IN A MULTI-CORE PROCESSOR
First Claim
1. A multi-core processor comprising:
- a plurality of physical processing cores; and
inter-core state discovery microcode in each core enabling the core to participate in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, sent to or received from other cores.
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Accused Products
Abstract
A multi-core processor includes microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process. In a related microcode-implemented method, states of a multi-core processor are discovered by at least two cores participating in a de-centralized inter-core state discovery process. The inter-core state discovery process is carried out through a combination of microcode executing on each participating core and signals exchanged between the cores through sideband non-system-bus communication wires. The discovery process is unmediated by any centralized non-core logic. Applicable discoverable states include target and composite power states, whether and how many cores are enabled, the availability and distribution of various resources, and hierarchical structures and coordination systems for the cores. The inter-core state discovery process may be carried out in accordance with various hierarchical coordination systems involving chained inter-core communications.
10 Citations
11 Claims
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1. A multi-core processor comprising:
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a plurality of physical processing cores; and inter-core state discovery microcode in each core enabling the core to participate in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, sent to or received from other cores. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A decentralized, microcode-implemented method of discovering states of a multi-core processor comprising a plurality of physical processing cores, the method comprising:
at least two cores participating in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, exchanged by the cores.
Specification