AUTOMATIC SELECTION OF ON-CHIP CLOCK IN SYNCHRONOUS DIGITAL SYSTEMS

• US 20140173324A1
• Filed: 12/13/2013
• Published: 06/19/2014
• Est. Priority Date: 12/13/2012
• Status: Active Grant

• Current Assignee: Coherent Logix, Incorporated
• Original Assignee: Coherent Logix, Incorporated
• Inventors: Dobbs, Carl S., Trocino, Michael R., Faulkner, Kenneth R., Schreppel, Christopher L.
• Granted Patent: US 9,325,329 B2
• Time in Patent Office: Days
• US Class Current: 713/501
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 11/1604 where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. A clock signal generated on-chip with the synchronous digital system may be automatically selected in response to detecting a condition indicating that use of a local clock may be necessary. Such conditions may include detection of tampering with the synchronous digital system. If an indication of tampering is detected, security measures may be performed.

Claims

1. A synchronous digital system comprised on a chip, the synchronous digital system comprising:

synchronous digital logic configured to operate using a primary clock signal;

an on-chip clock signal generator configured to generate a first clock signal independent of an external clock signal received by the synchronous digital system; and

clock signal selector circuitry configured to select between a plurality of clock signals for use as the primary clock signal, wherein the plurality of clock signals comprises the first clock signal and a signal dependent on the external clock signal, wherein the clock signal selector circuitry is further configured to;

when a clock selection override signal indicates normal operation, select between the plurality of clock signals based at least in part on the contents of a software-configurable register; and

when the clock selection override signal indicates a condition requiring selection of a clock signal generated on-chip for use as the primary clock signal, select the first clock signal.

2. The synchronous digital system of claim 1, wherein the clock selection override signal comprises a tamper detection signal, and wherein the clock selection override signal indicating a condition requiring selection of a clock signal generated on-chip for use as the primary clock signal comprises the tamper detection signal indicating possible tampering with the synchronous digital system.

3. The synchronous digital system of claim 2, wherein the synchronous digital logic is configured to:

perform, in response to the tamper detection signal indicating possible tampering with the synchronous digital system, security measures requiring a continuing clock signal, wherein the selecting the first clock signal enables the security measures to be performed regardless of whether the external clock signal is stopped.

4. The synchronous digital system of claim 3, wherein the security measures comprise clearing state information of the synchronous digital logic.

5. The synchronous digital system of claim 1, wherein the clock selection override signal comprises a clock-loss signal, and wherein the clock selection override signal indicating a condition requiring selection of a clock signal generated on-chip for use as the primary clock signal comprises the clock-loss signal indicating that loss of the external clock signal is anticipated.

6. The synchronous digital system of claim 1, wherein the on-chip clock signal generator comprises a ring oscillator.

7. The synchronous digital system of claim 1, wherein the clock signal selector circuitry is configured to programmatically select between the plurality of clock signals without causing clock-induced errors in the synchronous digital system.

8. The synchronous digital system of claim 7, wherein the clock signal selector circuitry comprises a de-glitched clock multiplexer configured to select between the plurality of clock signals for use as the primary clock signal.

9. A method of avoiding clock signal errors in a synchronous digital system comprised on a chip, the method comprising:

providing a first clock signal as a primary clock for the synchronous digital system, wherein the first clock signal is dependent upon an external clock signal received by the synchronous digital system;

receiving a clock selection override signal indicating a condition requiring selection of a clock signal generated on-chip for use as the primary clock;

selecting, in response to the receiving, a second clock signal as the primary clock, wherein the second clock signal is generated by an on-chip clock signal generator independent of the external clock signal.

10. The method of claim 9, wherein the receiving the clock selection override signal comprises receiving a tamper detection signal indicating possible tampering with the synchronous digital system.

11. The method of claim 10, further comprising performing, in response to the tamper detection signal indicating possible tampering with the synchronous digital system, security measures requiring a continuing clock signal, wherein the selecting the first clock signal enables the security measures to be performed regardless of whether the external clock signal is stopped.

12. The method of claim 11, wherein the performing the security measures comprises executing steps to clear state information of the synchronous digital system, wherein the second clock signal is used as the primary clock during the executing.

13. The method of claim 9, wherein the receiving the clock selection override signal comprises receiving a signal indicating that loss of the external clock signal is anticipated.

14. The method of claim 9, wherein the on-chip clock signal generator comprises a ring oscillator.

15. The method of claim 9, wherein the selecting the second clock signal as the primary clock is performed without causing clock-induced errors in the synchronous digital system.

16. The method of claim 15, wherein the selecting the second clock signal as the primary clock is performed by one or more de-glitched clock multiplexers.