THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME
First Claim
1. A thin film transistor array panel, comprising:
- a channel layer comprising an oxide semiconductor and formed in a semiconductor layer;
a source electrode formed in the semiconductor layer and connected to the channel layer at a first side of the channel layer;
a drain electrode formed in the semiconductor layer and connected to the channel layer at a second side of the channel layer, opposing the first side;
a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode;
an insulating layer disposed on the channel layer;
a gate line comprising a gate electrode disposed on the insulating layer;
a passivation layer disposed on the source electrode, the drain electrode, the pixel electrode, and the gate line; and
a data line disposed on the passivation layer,wherein a width of the channel layer is substantially equal to a width of the pixel electrode in a direction parallel to the gate line.
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Accused Products
Abstract
A thin film transistor array panel may include a channel layer including an oxide semiconductor and formed in a semiconductor layer, a source electrode formed in the semiconductor layer and connected to the channel layer at a first side, a drain electrode formed in the semiconductor layer and connected to the channel layer at an opposing second side, a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode, an insulating layer disposed on the channel layer, a gate line including a gate electrode disposed on the insulating layer, a passivation layer disposed on the source and drain electrodes, the pixel electrode, and the gate line, and a data line disposed on the passivation layer. A width of the channel layer may be substantially equal to a width of the pixel electrode in a direction parallel to the gate line.
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Citations
30 Claims
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1. A thin film transistor array panel, comprising:
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a channel layer comprising an oxide semiconductor and formed in a semiconductor layer; a source electrode formed in the semiconductor layer and connected to the channel layer at a first side of the channel layer; a drain electrode formed in the semiconductor layer and connected to the channel layer at a second side of the channel layer, opposing the first side; a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode; an insulating layer disposed on the channel layer; a gate line comprising a gate electrode disposed on the insulating layer; a passivation layer disposed on the source electrode, the drain electrode, the pixel electrode, and the gate line; and a data line disposed on the passivation layer, wherein a width of the channel layer is substantially equal to a width of the pixel electrode in a direction parallel to the gate line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of manufacturing a thin film transistor array panel, comprising:
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forming an oxide semiconductor layer on an insulation substrate; forming an insulating layer and a gate line comprising a gate electrode on the oxide semiconductor layer; forming a channel layer, a source electrode, a drain electrode, and a pixel electrode in the oxide semiconductor layer by performing a reduction process on an exposed portion of the oxide semiconductor layer, wherein the channel layer is covered by the gate electrode, the source electrode is formed at a first side of the channel layer, the drain electrode is formed at a second side of the channel layer, opposing the first side, the pixel electrode and the drain electrode are formed in a same portion of the oxide semiconductor layer, and the exposed portion of the oxide semiconductor layer is not covered by the insulating layer and the gate line; forming a passivation layer on the source electrode, the drain electrode, the pixel electrode, and the gate line; and forming a data line on the passivation layer, wherein a width of the channel layer is formed to be substantially equal to a width of the pixel electrode in a direction parallel to the gate line. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification