SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, POWER SUPPLY, AND HIGH-FREQUENCY AMPLIFIER

• US 20140175453A1
• Filed: 10/29/2013
• Published: 06/26/2014
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yamada, Atsushi
• Granted Patent: US 9,054,170 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7785 with more than one donor layer
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A semiconductor device includes: a first transistor that includes a first gate electrode, a first source electrode, a first drain electrode, and a first nitride semiconductor laminate that includes a first electron transit layer and a first electron supply layer; a second transistor that includes a second gate electrode, a second source electrode, a second drain electrode, and a second nitride semiconductor laminate that includes a second electrode transit layer and a second electron supply layer, the second drain electrode being a common electrode that also serves as the first source electrode, the second electron transit layer having part that underlies the second gate electrode and that contains a p-type dopant; and a p-type-dopant-diffusion-blocking layer.

Claims

1. A semiconductor device comprising:

a first transistor that includes a first gate electrode, a first source electrode, a first drain electrode, and a first nitride semiconductor laminate that includes a first electron transit layer and a first electron supply layer;

a second transistor that includes a second gate electrode, a second source electrode, a second drain electrode, and a second nitride semiconductor laminate that includes a second electrode transit layer and a second electron supply layer, the second drain electrode being a common electrode that also serves as the first source electrode, the second electron transit layer having part that underlies the second gate electrode and that contains a p-type dopant; and

a p-type-dopant-diffusion-blocking layer,

wherein

the second nitride semiconductor laminate is disposed higher than the first nitride semiconductor laminate with the p-type-dopant-diffusion-blocking layer interposed between the first and second nitride semiconductor laminates, and

the first gate electrode and the second source electrode are electrically coupled to each other to establish cascode connection of the first transistor to the second transistor.

2. The semiconductor device according to claim 1, wherein

the first electron supply layer is thicker than the second electron supply layer.

3. The semiconductor device according to claim 1, wherein

the distance between the first gate electrode and the first drain electrode is greater than the distance between the first gate electrode and the first source electrode.

4. The semiconductor device according to claim 1, wherein

the p-type-dopant-diffusion-blocking layer contains any one of AlGaN and AlN having an Al content of not less than 0.5.

5. The semiconductor device according to claim 1, wherein

the common electrode that serves as the first source electrode and the second drain electrode is formed of the same metal as used for forming the first drain electrode and the second source electrode.

6. The semiconductor device according to claim 1, wherein

the common electrode that serves as the first source electrode and the second drain electrode is an n-doped region that extends from the surface of the second nitride semiconductor laminate to the first electron transit layer.

7. The semiconductor device according to claim 1, wherein

the common electrode that serves as the first source electrode and the second drain electrode is an n-type semiconductor layer that extends from the surface of the second nitride semiconductor laminate to the surface of the first nitride semiconductor laminate.

8. The semiconductor device according to claim 1, wherein

the first electron transit layer contains GaN,

the first electron supply layer contains AlGaN,

the p-type-dopant-diffusion-blocking layer contains any one of AlGaN and AlN,

the second electron transit layer contains GaN and any one of Be, Mg, Fe, and C as the p-type dopant, and

the second electron supply layer contains any one of AlGaN, InAlN, and AlInGaN.

9. A power supply comprising:

a transistor chip that includes

a first transistor that includes a first gate electrode, a first source electrode, a first drain electrode, and a first nitride semiconductor laminate that includes a first electron transit layer and a first electron supply layer;

a second transistor that includes a second gate electrode, a second source electrode, a second drain electrode, and a second nitride semiconductor laminate that includes a second electrode transit layer and a second electron supply layer, the second drain electrode being a common electrode that also serves as the first source electrode, the second electron transit layer having part that underlies the second gate electrode and that contains a p-type dopant; and

a p-type-dopant-diffusion-blocking layer,

wherein

the second nitride semiconductor laminate is disposed higher than the first nitride semiconductor laminate with the p-type-dopant-diffusion-blocking layer interposed between the first and second nitride semiconductor laminates, and

the first gate electrode and the second source electrode are electrically coupled to each other to establish cascode connection of the first transistor to the second transistor.

10. A high-frequency amplifier comprising:

an amplifier that amplifies an input signal, the amplifier including a transistor chip that includes

a first transistor that includes a first gate electrode, a first source electrode, a first drain electrode, and a first nitride semiconductor laminate that includes a first electron transit layer and a first electron supply layer;

a second transistor that includes a second gate electrode, a second source electrode, a second drain electrode, and a second nitride semiconductor laminate that includes a second electrode transit layer and a second electron supply layer, the second drain electrode being a common electrode that also serves as the first source electrode, the second electron transit layer having part that underlies the second gate electrode and that contains a p-type dopant; and

a p-type-dopant-diffusion-blocking layer,

wherein

the second nitride semiconductor laminate is disposed higher than the first nitride semiconductor laminate with the p-type-dopant-diffusion-blocking layer interposed between the first and second nitride semiconductor laminates, and

the first gate electrode and the second source electrode are electrically coupled to each other to establish cascode connection of the first transistor to the second transistor.

11. A method for manufacturing a semiconductor device, the method comprising:

forming a first nitride semiconductor laminate that includes a first electron transit layer and a first electron supply layer, a p-type-dopant-diffusion-blocking layer, and a second nitride semiconductor laminate that includes a second electron transit layer and a second electron supply layer, each layer overlying a semiconductor substrate, the second electron transit layer containing a p-type dopant;

removing part of the second nitride semiconductor laminate corresponding to a region in which a first transistor is to be formed, the first transistor including a first gate electrode, a first source electrode, a first drain electrode, and the first nitride semiconductor laminate;

forming the first drain electrode such that the first drain electrode overlies the first nitride semiconductor laminate in the region in which the first transistor is to be formed and forming a second source electrode such that the second source electrode overlies the second nitride semiconductor laminate in a region in which a second transistor is to be formed, the second transistor including a second gate electrode, the second source electrode, a second drain electrode, and the second nitride semiconductor laminate;

forming a common electrode that serves as the first source electrode and the second drain electrode;

forming the first gate electrode such that the first gate electrode overlies the first nitride semiconductor laminate and forming the second gate electrode such that the second gate electrode overlies the second nitride semiconductor laminate; and

electrically coupling the first gate electrode to the second source electrode to establish cascode connection of the first transistor to the second transistor.

12. The method according to claim 11, wherein

the first electron supply layer is formed so as to be thicker than the second electron supply layer.

13. The method according to claim 11, wherein

the first gate electrode, the first drain electrode, and the first source electrode are formed such that the distance between the first gate electrode and the first drain electrode is greater than the distance between the first gate electrode and the first source electrode.

14. The method according to claim 11, wherein

the p-type-dopant-diffusion-blocking layer is formed of any one of AlGaN and AlN having an Al content of not less than 0.5.

15. The method according to claim 11, wherein

the common electrode that serves as the first source electrode and the second drain electrode is formed of the same metal as used for forming the first drain electrode and the second source electrode.

16. The method according to claim 11, wherein

an n-doped region that extends from the surface of the second nitride semiconductor laminate to the first electron transit layer is formed as the common electrode that serves as the first source electrode and the second drain electrode.

17. The method according to claim 11, wherein

an n-type semiconductor layer that extends from the surface of the second nitride semiconductor laminate to the surface of the first nitride semiconductor laminate is formed as the common electrode that serves as the first source electrode and the second drain electrode.

18. The method according to claim 11, wherein

the first electron transit layer contains GaN,

the first electron supply layer contains AlGaN,

the p-type-dopant-diffusion-blocking layer contains any one of AlGaN and AlN,

the second electron transit layer contains GaN and any one of Be, Mg, Fe, and C as the p-type dopant, and

the second electron supply layer contains any one of AlGaN, InAlN, and AlInGaN.