INTEGRATED DEVICE HAVING MOSFET CELL ARRAY EMBEDDED WITH BARRIER SCHOTTKY DIODE
First Claim
1. An integrated device having a metal oxide semiconductor field effect transistor (MOSFET) cell array embedded with a junction barrier Schottky (JBS) diode, comprising a plurality of areas, each area comprising:
- a plurality of MOS transistor cells, wherein any two adjacent MOS transistor cells are separated by a separating line, and wherein a first MOS transistor cell and a second MOS transistor cell are adjacent in a first direction and separated by a first separating line, and the first transistor cell and a third MOS transistor cell are adjacent in a second direction and separated by a second separating line; and
at least one JBS diode, disposed at an intersection region between the first separating line and the second separating line, wherein the JBS diode is connected in anti-parallel to the first, second and third MOS transistor cells.
1 Assignment
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Accused Products
Abstract
Provided is an integrated device having a MOSFET cell array embedded with a junction barrier Schottky (JBS) diode. The integrated device comprises a plurality of areas, each of which includes a plurality of MOS transistor cells and at least one JBS diode. Any two adjacent MOS transistor cells are separated by a separating line. A first MOS transistor cell and a second MOS transistor cell are adjacent in a first direction and separated by a first separating line, and the first transistor cell and a third MOS transistor cell are adjacent in a second direction and separated by a second separating line. The JBS diode is disposed at an intersection region between the first separating line and the second separating line. The JBS diode is connected in anti-parallel to the first, second and third MOS transistor cells.
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Citations
18 Claims
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1. An integrated device having a metal oxide semiconductor field effect transistor (MOSFET) cell array embedded with a junction barrier Schottky (JBS) diode, comprising a plurality of areas, each area comprising:
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a plurality of MOS transistor cells, wherein any two adjacent MOS transistor cells are separated by a separating line, and wherein a first MOS transistor cell and a second MOS transistor cell are adjacent in a first direction and separated by a first separating line, and the first transistor cell and a third MOS transistor cell are adjacent in a second direction and separated by a second separating line; and at least one JBS diode, disposed at an intersection region between the first separating line and the second separating line, wherein the JBS diode is connected in anti-parallel to the first, second and third MOS transistor cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification