SEMICONDUCTOR SUBSTRATE FOR PHOTONIC AND ELECTRONIC STRUCTURES AND METHOD OF MANUFACTURE

• US 20140175596A1
• Filed: 01/09/2014
• Published: 06/26/2014
• Est. Priority Date: 12/26/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Meade, Roy, Sandhu, Gurtej
• Granted Patent: US 8,815,704 B2
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: G02B 2006/121 Channel; buried or the like
• CPC Class Codes: G02B 6/1225 comprising photonic band-gap structures or photonic lattices
• CPC Class Codes: G02B 6/13 Integrated optical circuits characterised by the manufacturing method
• CPC Class Codes: G02B 6/136 by etching
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps

Abstract

A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and photolithographic technique is used to fabricate a mask defining openings for etching first and second trench isolation areas in a substrate, with the openings for the second trench isolation areas being wider than the openings for the first trench isolation areas. The first and second trench isolation areas are etched in the substrate through the mask. The second trench isolation areas are further etched to the deeper than the first trench isolation areas. The trench isolation areas are filled with oxide material. Electrical devices can be formed on the substrate and electrically isolated by the first trench isolation areas and photonic devices can be formed over the second trench isolation areas and be optically isolated from the substrate.

Claims

1. A method of forming an integrated structure, the method comprising:

forming an etch mask material over a semiconductor substrate;

using a single reticle in a photolithographic process to pattern the etch mask material to define a first and a second opening for forming a first and a second trench isolation area, the second opening being wider than the first opening;

etching first and second trench isolation areas in the semiconductor substrate using the patterned etch mask material;

processing the etched first and second trench isolation areas to produce first and second trench isolation areas, filled with a dielectric material, the second dielectric filled trench isolation area being deeper than the dielectric filled first trench isolation area;

forming a photonic device over the dielectric filled second trench isolation area such that the photonic device is optically isolated from the substrate.

2. A method as in claim 1, further comprising planarizing to the level of an upper surface of the substrate after the first trench isolation area and second trench isolation areas are filled with dielectric.

3. A method as in claim 2, wherein the semiconductor substrate comprises a silicon substrate.

4. A method as in claim 2, further comprising forming an oxide between the etch mask material and substrate, wherein the single reticle and photolithograph process patterns the etch mask material and pad oxide.

5. A method as in claim 1, wherein the dielectric material comprises an oxide.

6. A method as in claim 1, wherein the processing produces a second trench isolation area which is at least twice as deep as the first trench isolation area.

7. A method as in claim 6, wherein the first trench isolation area is about 200 nm to about 300 nm deep.

8. A method as in claim 6, wherein the second trench isolation area is about 1.2 μ

m to about 1.5 μ

m deep.

9. A method of forming an integrated structure, the method comprising:

using a single reticle in a photolithographic process to pattern an etch mask provided over a semiconductor substrate, the pattern defining openings for etching first trench isolation areas and at least one second trench isolation area in the substrate, the opening for etching the at least one second trench isolation area being wider than the openings for etching the first trench isolation areas;

removing semiconductor material from the substrate using the first and second openings in the etch mask to provide the first and second trench isolation areas;

further etching the at least one second trench isolation area to be deeper than the first trench isolation areas;

filling the first and second trench isolation areas with a dielectric material;

planarizing the first and second trench isolation areas to the level of the substrate; and

,

forming a photonic device on the at least one planarized second trench isolation area.

10. A method as in claim 9, wherein the first trench isolation areas have a width of about 20 nm to about 150 nm.

11. A method as in claim 9, wherein the at least one second trench isolation area has a width of about 2 μ

m to about 10 μ

m.

12. A method as in claim 11, wherein the at least one second trench isolation area has a width of about 2 μ

m to about 4 μ

m.

13. The method as in claim 9, wherein the at least one second trench isolation area is etched to be at least twice as deep as the first trench isolation areas.

14. The method as in claim 9, further comprising fabricating optical isolation areas on the sides and over the photonic device.

15. The method as in claim 14, wherein the optical isolation areas are part of an interlayer dielectric structure.

16. A method of forming an integrated structure, the method comprising:

forming first and second dielectric filled trench isolation areas in a semiconductor substrate, which have upper surfaces which are planar with the upper surface of the substrate, the second isolation area being wider and deeper than the first isolation area, the locations of the first and second dielectric filled trench isolation areas being defined by a hard mask patterned by a single reticle;

forming an electronic device on the substrate which is electrically isolated by the first trench isolation area; and

forming a photonic device on the second trench isolation area, the photonic device being optically isolated from the substrate by the second trench isolation area.

17. An integrated circuit structure comprising:

a semiconductor substrate having a planar upper surface;

a first trench isolation area having a first depth into the substrate from the planar upper surface;

an electronic device electrically isolated by the first trench isolation area;

a second trench isolation area having a second depth into the substrate from the planar upper surface, where the second depth is greater than the first depth, the second trench isolation area having a planar upper surface; and

a photonic device on the planar upper surface of the second trench isolation area, the photonic device being optically isolated from the substrate by the second trench isolation area.

18. An integrated circuit structure as in claim 17, wherein the second trench area does not extend through the entirety of the substrate.

19. An integrated circuit structure as in claim 17, wherein the second trench isolation area is at least twice as deep as the first trench isolation area.

20. An integrated circuit structure as in claim 17, wherein the second trench isolation area has a depth in the range of about 1.2 um to about 1.5 um deep.

21. An integrated circuit structure as in claim 17, wherein the width of the second trench isolation area is greater than the width of the first trench isolation area.

22. An integrated circuit structure as in claim 21, wherein the width of the second trench isolation area is greater than twice the width of the first trench isolation area.

23. An integrated circuit structure as in claim 22, wherein the width of the first trench isolation area is in the range of about 20 nm to about 150 nm and the width of the second trench isolation area is in the range of about 2 um to about 10 um.

24. An integrated circuit structure as in claim 23, wherein the second trench isolation area has a width in the range of about 2 um to about 4 um.