Semiconductor Device and Method of Bonding Semiconductor Die to Substrate in Reconstituted Wafer Form

• US 20140175640A1
• Filed: 09/27/2013
• Published: 06/26/2014
• Est. Priority Date: 12/20/2012
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac Limited
• Inventors: Marimuthu, Pandi C., Anderson, Steve, Chi, HeeJo, Kim, KyungMoon, Lee, KooHong, Yee, JaeHak, Kim, YoungChul, Hoang, Lan, Lee, HunTeak
• Granted Patent: US 9,287,204 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/7598 : specially adapted for batch processes
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/83102 : using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3142 : Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.

Claims

1. A method of making a semiconductor device, comprising:

providing a plurality of semiconductor die;

providing a carrier;

disposing the semiconductor die over the carrier;

providing a substrate; and

bonding the semiconductor die to the substrate while disposed over the carrier.

2. The method of claim 1, further including forming an electrical interconnect over the semiconductor die.

3. The method of claim 2, wherein the electrical interconnect includes a stud bump.

4. The method of claim 2, further including forming a bump over the substrate.

5. The method of claim 1, further including bonding the semiconductor die to the substrate using thermocompression.

6. The method of claim 1, further including depositing an underfill material between the semiconductor die and substrate.

7. A method of making a semiconductor device, comprising:

providing a plurality of semiconductor die;

providing a carrier;

disposing the semiconductor die over the carrier; and

forming an electrical interconnect over the semiconductor die while disposed over the carrier.

8. The method of claim 7, further including:

providing a substrate; and

bonding the semiconductor die to the substrate while disposed over the carrier.

9. The method of claim 8, further including depositing an underfill material between the semiconductor die and substrate.

10. The method of claim 8, further including depositing an encapsulant over the semiconductor die and substrate.

11. The method of claim 8, further including forming a bump over the substrate.

12. The method of claim 8, further including bonding the semiconductor die to the substrate using thermocompression.

13. The method of claim 7, wherein the electrical interconnect includes a stud bump.

14. A semiconductor device, comprising:

a carrier;

a plurality of semiconductor die disposed over the carrier; and

a substrate, wherein the semiconductor die is bonded to the substrate while disposed over the carrier.

15. The semiconductor device of claim 14, further including an electrical interconnect formed over the semiconductor die.

16. The semiconductor device of claim 15, wherein the electrical interconnect includes a stud bump.

17. The semiconductor device of claim 14, further including a bump formed over the substrate.

18. The semiconductor device of claim 14, wherein the semiconductor die is thermocompression bonded to the substrate.

19. The semiconductor device of claim 14, further including an underfill material deposited between the semiconductor die and substrate.

20. A semiconductor device, comprising:

a carrier;

a plurality of semiconductor die disposed over the carrier; and

an electrical interconnect formed over the semiconductor die while disposed over the carrier.

21. The semiconductor device of claim 20, further including a substrate, wherein the semiconductor die is bonded to the substrate while disposed over the carrier.

22. The semiconductor device of claim 21, further including an encapsulant deposited over the semiconductor die and substrate.

23. The semiconductor device of claim 21, further including a bump formed over the substrate.

24. The semiconductor device of claim 21, wherein the semiconductor die is thermocompression bonded to the substrate.

25. The semiconductor device of claim 20, wherein the electrical interconnect includes a stud bump.