SWITCH CIRCUIT AND SPDT SWITCH CIRCUIT

• US 20140175901A1
• Filed: 12/24/2013
• Published: 06/26/2014
• Est. Priority Date: 12/26/2012
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Park, Sung Hwan, CHOI, Jae Hyouck
• Granted Patent: US 9,705,492 B2
• Time in Patent Office: Days
• US Class Current: 307/113
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

The present invention relates to a switch circuit and a single pole double throw (SPDT) circuit. The switch circuit includes: a MOS transistor transferring or blocking a signal according to a turn on/off operation thereof; a gate resistor connected to a gate of the MOS transistor; and a variable gate resistor circuit increasing a resistance value of the gate resistor when the MOS transistor is changed from a turn-off state to a turn-on state.

Claims

1. A switch circuit comprising:

a metal oxide semiconductor (MOS) transistor transferring or blocking a signal according to a turn on/off operation thereof;

a gate resistor connected to a gate of the MOS transistor; and

a variable gate resistor circuit increasing a resistance value of the gate resistor when the MOS transistor is changed from a turn-off state to a turn-on state.

2. The switch circuit according to claim 1, wherein the variable gate resistor circuit includes a series additional resistor and a first transistor turned on at the time of applying turn-on gate power of the MOS transistor to connect the series additional resistor in series with the gate resistor, thereby increasing the resistance value of the gate resistor.

3. The switch circuit according to claim 2, wherein the variable gate resistor circuit further includes a second transistor connected in parallel with the first transistor and turned on at the time of applying turn-off gate power of the MOS transistor to turn off the MOS transistor.

4. The switch circuit according to claim 3, wherein each of the MOS transistor, the first transistor, and the second transistor is an N-channel MOS (NMOS) transistor.

5. The switch circuit according to claim 3, wherein each of the MOS transistor and the first transistor is an NMOS transistor, and

the second transistor is a P-channel MOS (PMOS) transistor.

6. The switch circuit according to claim 1, wherein the MOS transistor forms a signal transfer switch of a single pole double throw (SPDT) circuit.

7. A switch circuit comprising:

a MOS transistor transferring or blocking a signal according to a turn on/off operation thereof;

a gate resistor connected to a gate of the MOS transistor; and

a variable gate resistor circuit decreasing a resistance value of the gate resistor when the MOS transistor is changed from a turn-on state to a turn-off state.

8. The switch circuit according to claim 7, wherein the variable gate resistor circuit includes:

a parallel additional resistor connected in parallel with the gate resistor; and

third and fourth transistors turned on at the time of applying turn-off gate power of the MOS transistor to connect the gate resistor and the parallel additional resistor in parallel with each other, thereby decreasing the resistance value of the gate resistor and turning off the MOS transistor.

9. The switch circuit according to claim 8, wherein the variable gate resistor circuit further includes a fifth transistor turned on at the time of applying turn-on gate power of the MOS transistor to turn on the MOS transistor through the gate resistor.

10. The switch circuit according to claim 9, wherein each of the MOS transistor, the third transistor, the fourth transistor, and the fifth transistor is an NMOS transistor.

11. The switch circuit according to claim 9, wherein each of the MOS transistor and the fifth transistor is an NMOS transistor, and

each of the third and fourth transistors is a PMOS transistor.

12. The switch circuit according to claim 7, wherein the MOS transistor forms a signal transfer switch of an SPDT circuit.

13. An SPDT circuit comprising:

an antenna;

a first MOS transistor group transmitting a transmission signal from a transmitting end to the antenna according to a turn-on operation thereof and blocking introduction of a reception signal received in the antenna into the transmitting end according to a turn-off operation thereof;

a first gate resistor group including gate resistors each connected to gates of the respective transistors of the first MOS transistor group;

a second MOS transistor group applied with gate power complementary to turn-on gate power of the first MOS transistor group to operate complementarily to the first MOS transistor group, transferring the reception signal to a receiving end, and blocking leakage of the transmission signal to the receiving end;

a second gate resistor group including gate resistors each connected to gates of the respective transistors of the second MOS transistor group; and

a variable gate resistor circuit group increasing resistance values of the respective gate resistors when each of the first and second MOS transistor groups is changed from a turn-off state to a turn-on state.

14. The SPDT circuit according to claim 13, wherein the variable gate resistor circuit group includes a first variable gate resistor circuit increasing the resistance values of the respective gate resistors when the first MOS transistor group is changed from a turn-off state to a turn-on state;

and a second variable gate resistor circuit increasing the resistance values of the respective gate resistors when the second MOS transistor group is changed from a turn-off state to a turn-on state,

the first variable gate resistor circuit including a first series additional resistor;

a first transistor turned on at the time of applying turn-on gate power of the first MOS transistor group to connect the first series additional resistor in series with the respective gate resistors of the first MOS transistor group, thereby increasing the resistances value of the gate resistors; and

a second transistor connected in parallel with the first transistor and turned on at the time of applying turn-off gate power of the first MOS transistor group to turn off the first MOS transistor group, and

the second variable gate resistor circuit including a second series additional resistor;

an eleventh transistor turned on at the time of applying turn-on gate power of the second MOS transistor group to connect the second series additional resistor in series with the respective gate resistors of the second MOS transistor group, thereby increasing the resistances value of the gate resistors; and

a twelfth transistor connected in parallel with the eleventh transistor and turned on at the time of applying turn-off gate power of the second MOS transistor group to turn off the second MOS transistor group.

15. The SPDT circuit according to claim 14, wherein in each of the first and second MOS transistor groups, NMOS transistors are connected to one another in a cascode structure, and

each of the first, second, eleventh, and twelfth transistors is an NMOS transistor.

16. The SPDT circuit according to claim 14, wherein in each of the first and second MOS transistor groups, NMOS transistors are connected to one another in a cascode structure,

each of the first and eleventh transistors is an NMOS transistor, and

each of the second and twelfth transistors is a PMOS transistor.

17. An SPDT circuit comprising:

an antenna;

a first MOS transistor group transmitting a transmission signal from a transmitting end to the antenna according to a turn-on operation thereof and blocking introduction of a reception signal received in the antenna into the transmitting end according to a turn-off operation thereof;

a first gate resistor group including gate resistors each connected to gates of the respective transistors of the first MOS transistor group;

a second MOS transistor group applied with gate power complementary to turn-on gate power of the first MOS transistor group to operate complementarily to the first MOS transistor group, transferring the reception signal to a receiving end, and blocking leakage of the transmission signal to the receiving end;

a second gate resistor group including gate resistors each connected to gates of the respective transistors of the second MOS transistor group; and

a variable gate resistor circuit group decreasing resistance values of the respective gate resistors when each of the first and second MOS transistor groups is changed from a turn-on state to a turn-off state.

18. The SPDT circuit according to claim 17, wherein the variable gate resistor circuit group includes a third variable gate resistor circuit decreasing the resistance values of the respective gate resistors when the first MOS transistor group is changed from a turn-on state to a turn-off state;

and a fourth variable gate resistor circuit decreasing the resistance values of the respective gate resistors when the second MOS transistor group is changed from a turn-on state to a turn-off state,

the third variable gate resistor circuit including a third parallel additional resistor group including parallel additional resistors connected in parallel with the respective gate resistors of the first MOS transistor group;

third and fourth transistors turned on at the time of applying turn-off gate power of the first MOS transistor group to connect the respective gate resistors and the respective parallel additional resistors of the third parallel additional resistor group in parallel with each other, thereby decreasing the resistance values of the respective gate resistors and turning off the first MOS transistor group; and

a fifth transistor turned on at the time of applying turn-on gate power of the first MOS transistor group to turn on the first MOS transistor group through the respective gate resistors, and

the fourth variable gate resistor circuit including a fourth parallel additional resistor group including parallel additional resistors connected in parallel with the respective gate resistors of the second MOS transistor group;

thirteenth and fourteenth transistors turned on at the time of applying turn-off gate power of the second MOS transistor group to connect the respective gate resistors and the respective parallel additional resistors of the fourth parallel additional resistor group in parallel with each other, thereby decreasing the resistance values of the respective gate resistors and turning off the second MOS transistor group; and

a fifteenth transistor turned on at the time of applying turn-on gate power of the second MOS transistor group to turn on the second MOS transistor group through the respective gate resistors.

19. The SPDT circuit according to claim 18, wherein in each of the first and second MOS transistor group, NMOS transistors are connected to one another in a cascode structure, and

each of the third, fourth, fifth, thirteenth, fourteenth, and fifteenth transistors is an NMOS transistor.

20. The SPDT circuit according to claim 18, wherein in each of the first and second MOS transistor group, NMOS transistors are connected to one another in a cascode structure,

each of the third, fourth, thirteenth, and fourteenth transistors is a PMOS transistor, and

each of the fifth and fifteenth transistors is an NMOS transistor.