Phase locked loop system and working method thereof

• US 20140176204A1
• Filed: 10/24/2013
• Published: 06/26/2014
• Est. Priority Date: 10/24/2012
• Status: Abandoned Application

• Current Assignee: IPGoal Microelectronics (Sichuan) Co., Ltd.
• Original Assignee: IPGoal Microelectronics (Sichuan) Co., Ltd.
• Inventors: Fan, Fangping
• Application Number:
  US14/062,772
• Publication Number:
  US 20140176204A1
• Time in Patent Office: Days
• US Class Current: 327/156
• CPC Class Codes: H03L 7/235 Nested phase locked loops

Abstract

A PLL system includes: an input end; an output end; a first PFD; a first CHP connected to the first PFD; a first LPF connected to the first CHP; a first VCO connected to the first CHP and the first LPF; a second PFD connected to the first VCO; a second CHP connected to the second PFD; a second LPF connected to the second CHP; a second VCO connected to the second CHP and the second LPF; a first DIV connected to the first PFD and the second VCO; and a second DIV connected to the second PFD and the second VCO. A working method of the PLL system is also provided, which can restrain input noise as well as phase noise of the second VOC in such a manner that noise of the PLL system is well restrained.

Claims

1. A PLL system, comprising:

an input end;

a first PFD connected to said input end;

a first CHP connected to said first PFD;

a first LPF connected to said first CHP;

a first VCO connected to said first CHP and said first LPF;

a second PFD connected to said first VCO;

a second CHP connected to said second PFD;

a second LPF connected to said second CHP;

a second VCO connected to said second CHP and said second LPF;

an output end connected to said second VCO;

a first DIV connected to said first PFD, said second VCO and said output end; and

a second DIV connected to said second PFD, said second VCO and said output end.

2. The PLL system, as recited in claim 1, wherein said second PFD, said second CHP, said second LPF, said second VCO and said second DIV form an inner loop;

and said inner loop, said first PFD, said first CHP, said first LPF, said first VCO and said first DIV form an outer loop.

3. The PLL system, as recited in claim 2, wherein said PLL system has a nested structure.

4. The PLL system, as recited in claim 1, wherein said input end and a first end of said first DIV are connected to a first end of said first PFD;

a second end of said first PFD is connected to a first end of said first CHP;

a second end of said first CHP is respectively connected to said first LPF and a first end of said first VOC;

a second end of said first VOC and a first end of said second DIV are connected to a first end of said second PFD;

a second end of said second PFD is connected to a first end of said second CHP;

a second end of said second CHP is respectively connected to said second LPF and a first end of said second VOC;

a second end of said second VOC is respectively connected to a second end of said first DIV, a second end of said DIV and said output end.

5. A working method of a PLL system, wherein said PLL system comprises:

an input end;

a first PFD connected to said input end;

a first CHP connected to said first PFD;

a first LPF connected to said first CHP;

a first VCO connected to said first CHP and said first LPF;

a second PFD connected to said first VCO;

a second CHP connected to said second PFD;

a second LPF connected to said second CHP;

a second VCO connected to said second CHP and said second LPF;

an output end connected to said second VCO;

a first DIV connected to said first PFD, said second VCO and said output end; and

a second DIV connected to said second PFD, said second VCO and said output end.

6. The method, as recited in claim 5, comprising steps of:

a) inputting a Fin through the input end, and inputting the Fin as well as a Fb1 into the first PFD, comparing a phase of the Fin with a phase of the Fb1 by the first PFD, then outputting a Vup1 and a Vdn1;

b) charging or discharging the first LPF by the first CHP under control of the Vup1 and the Vdn1 for generating a Vc1;

at the meantime, filtering the Vc1 by the first LPF for stabilizing the Vc1;

c) taking the Vc1 as a control voltage of the first VOC, and transforming the Vc1 into a Fs by the first VOC;

d) inputting the Fs and a Fb2 into the second PFD, comparing a phase of the Fs with a phase of the Fb2 by the second PFD, then outputting a Vup2 and a Vdn2;

e) charging or discharging the second LPF by the second CHP under control of the Vup2 and the Vdn2 for generating a Vc2;

at the meantime, filtering the Vc2 by the second LPF for stabilizing the Vc2;

f) taking the Vc2 as a control voltage of the second VOC, and transforming the Vc2 into a Fout by the second VOC;

g) dividing the Fout by the second DIV for obtaining the Fb2;

continuously comparing the Fb2 with the Fs by the second PFD and gradually adjusting an inner loop until the phase of the Fb2 is completely the same as the phase of the Fs; and

h) dividing the Fout by the first DIV for obtaining the Fb1;

continuously comparing the phase of the Fb1 with the phase of the Fout by the first PFD and gradually adjusting an outer loop until the phase of the Fb1 is completely the same as the phase of the Fin.

7. The method, as recited in claim 6, wherein the step b) specifically comprises:

inputting the Vup1 and the Vdn1 into the first CHP, and charging or discharging the first LPF by the first CHP under the control of the Vup1 and the Vdn1 for generating the Vc1, then increasing or decreasing the Vc1, wherein if the Vup1 is at a high level and the Vdn1 is at a low level, the first CHP charges the first LPF for increasing the Vc1;

if the Vup1 is at a low level and the Vdn1 is at a high level, the first CHP discharges the first LPF for decreasing the Vc1;

at the meantime, filtering the Vc1 by the first LPF for decreasing high dither of the Vc1 and stabilizing the Vc1.

8. The method, as recited in claim 6, wherein the step e) specifically comprises:

inputting the Vup2 and the Vdn2 into the second CHP, and charging or discharging the second LPF by the second CHP under the control of the Vup2 and the Vdn2 for generating the Vc2, then increasing or decreasing the Vc2, wherein if the Vup2 is at a high level and the Vdn2 is at a low level, the second CHP charges the second LPF for increasing the Vc2;

if the Vup2 is at a low level and the Vdn2 is at a high level, the second CHP discharges the second LPF for decreasing the Vc2;

at the meantime, filtering the Vc2 by the second LPF for decreasing high dither of the Vc2 and stabilizing the Vc2.