ADAPTIVE CONTROL MECHANISMS TO CONTROL INPUT AND OUTPUT COMMON-MODE VOLTAGES OF DIFFERENTIAL AMPLIFIER CIRCUITS

• US 20140176239A1
• Filed: 12/24/2012
• Published: 06/26/2014
• Est. Priority Date: 12/24/2012
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Duggal, Abhishek
• Application Number:
  US13/726,282
• Publication Number:
  US 20140176239A1
• Time in Patent Office: Days
• US Class Current: 330/260
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45744 by offset reduction

Abstract

An amplifier circuit includes differential input nodes, a differential amplifier stage having differential input terminals and differential output terminals, and an input common-mode voltage adaptation circuit connected between the differential input nodes of the amplifier circuit and the differential input terminals of the differential amplifier stage. During an input common-mode adaptation phase, the input common-mode voltage adaptation circuit forces the differential input terminals of the differential amplifier stage to a common-mode voltage equal to an adaptive reference voltage, independent of a common-mode voltage applied to the differential input nodes of the amplifier circuit during the input common-mode adaptation phase. During a normal period of operation of the amplifier circuit, the input common-mode voltage adaptation circuit maintains the common-mode voltage at the differential input terminals of the differential amplifier stage equal to the adaptive reference voltage, independent of an input differential voltage applied during the normal period of operation.

Claims

1. An amplifier circuit, comprising:

differential input nodes comprising first and second differential input nodes;

a differential amplifier stage comprising differential input terminals and differential output terminals; and

an input common-mode voltage adaptation circuit connected between the differential input nodes of the amplifier circuit and the differential input terminals of the differential amplifier stage,

wherein during an input common-mode adaptation phase, the input common-mode voltage adaptation circuit forces the differential input terminals of the differential amplifier stage to have a common-mode voltage equal to an adaptive reference voltage, independent of a common-mode voltage applied to the differential input nodes of the amplifier circuit during the input common-mode adaptation phase, and

wherein during a normal period of operation of the amplifier circuit, the input common-mode voltage adaptation circuit maintains the common-mode voltage at the differential input terminals of the differential amplifier stage equal to the adaptive reference voltage, independent of an input differential voltage applied during the normal period of operation.

2. The amplifier circuit of claim 1, wherein the input common-mode voltage adaption circuit comprises:

a first output node connected to a first differential input terminal of the differential amplifier stage;

a second output node connected to a second differential input terminal of the differential amplifier stage;

a first capacitor connected between the first differential input node of the amplifier circuit and the first output node;

a second capacitor connected between the second differential input node of the amplifier circuit and the second output node;

an adaptive reference voltage circuit to generate the adaptive reference voltage on a reference voltage node;

a first switch connected between the reference voltage node and the first output node; and

a second switch connected between the reference voltage node and the second output node,

wherein during the input common-mode adaptation phase, the input common-mode voltage adaptation circuit switchably connects the reference voltage node to the first and second output nodes to apply the adaptive reference voltage to both of the first and second differential input terminals of the differential amplifier stage.

3. The amplifier circuit of claim 2, wherein the adaptive reference voltage circuit comprises a diode-connected MOS transistor connected to the adaptive reference voltage node.

4. A system-on-chip comprising the amplifier circuit of claim 1.

5. An amplifier circuit, comprising:

differential input nodes comprising first and second differential input nodes;

a differential amplifier stage comprising differential input terminals and differential output terminals, the differential input terminals comprising first and second differential input terminals and the differential output terminals comprising first and second differential output terminals; and

an input common-mode voltage adaptation circuit connected between the differential input nodes of the amplifier circuit and the differential input terminals of the differential amplifier stage, the input common-mode voltage adaptation circuit comprising;

first and second feedback nodes connected to the first and second differential output terminals of the differential amplifier stage; and

first and second output nodes connected to the first and second differential input terminals of the differential amplifier stage,

wherein during a first portion of an input common-mode adaptation phase, the input common-mode voltage adaptation circuit applies an adaptive reference voltage to both the first and second differential input terminals of the differential amplifier stage to force the differential input terminals to have a common-mode voltage equal to the adaptive reference voltage, independent of a common-mode voltage applied to the differential input nodes of the amplifier circuit during the first portion of the input common-mode adaptation phase, and

wherein during a second portion of the input common-mode adaptation phase, the input common-mode voltage adaptation circuit capacitively couples the first and second differential output terminals of the differential amplifier stage to the first and second differential input terminals of the differential amplifier stage to generate a differential input voltage to perform offset cancellation, while maintaining the common-mode voltage at the differential input terminals of the differential amplifier stage.

6. The amplifier circuit of claim 5, wherein the input common-mode voltage adaption circuit comprises:

a first reference voltage node that receives a common-mode reference voltage;

a first switch connected between the first reference voltage node and the first feedback node;

a second switch connected between the first reference voltage node and the second feedback node;

a third switch connected between the first feedback node and the second differential output terminal;

a fourth switch connected between the second feedback node and the first differential output terminal;

a first capacitor connected between the first feedback node and the second output node;

a second capacitor connected between the second feedback node and the first output node;

a third capacitor connected between the first differential input node and the second output node;

a fourth capacitor connected between the second differential input node and the first output node;

an adaptive reference voltage circuit to generate the adaptive reference voltage on a second reference voltage node;

a fifth switch connected between the second reference voltage node and the second output node; and

a sixth switch connected between the second reference voltage node and the first output node.

7. The amplifier circuit of claim 6, wherein the adaptive reference voltage circuit comprises a diode-connected MOS transistor connected to the second reference voltage node.

8. The amplifier circuit of claim 6,

wherein during the first potion of the input common-mode adaptation phase, the fifth and sixth switches are activated to connect the second reference voltage node to the first and second output nodes of the input common-mode voltage adaptation circuit and apply the adaptive reference voltage to both the first and second differential input terminals of the differential amplifier stage, and the first and second switches are activated to connect the first and second feedback nodes to the first reference voltage node, and pre-charge the first and second capacitors to a voltage equal to the common-mode reference voltage less the adaptive reference voltage;

wherein during the second portion of the input common-mode adaptation phase, the first, second, fifth and sixth switches are deactivated, and the third and fourth switches are activated to capacitively couple the first differential output terminal to the first differential input terminal of the differential amplifier stage via the second capacitor, and to capacitively couple the second differential output terminal to the second differential input terminal of the differential amplifier stage via the first capacitor, and

wherein during a normal operating period of the amplifier circuit following the input common-mode adaption phase, the first, second, third, fourth, fifth and sixth switches are deactivated, and the first and second input nodes of the amplifier circuit are capacitively coupled to the second and first differential input terminals of the differential amplifier stage via the third and fourth capacitors, respectively.

9. The amplifier circuit of claim 5, wherein the input common-mode voltage adaption circuit comprises:

a first reference voltage node that receives a common-mode reference voltage;

a first switch connected between the first reference voltage node and the first feedback node;

a second switch connected between the first reference voltage node and the second feedback node;

a third switch connected between the first feedback node and the second differential output terminal;

a fourth switch connected between the second feedback node and the first differential output terminal;

a first capacitor connected between the first feedback node and the second output node;

a second capacitor connected between the second feedback node and the first output node;

a third capacitor connected between the first differential input node and the first feedback node;

a fourth capacitor connected between the second differential input node and the second feedback node;

an adaptive reference voltage circuit to generate the adaptive reference voltage on a second reference voltage node;

a fifth switch connected between the second reference voltage node and the second output node; and

a sixth switch connected between the second reference voltage node and the first output node.

10. The amplifier circuit of claim 9, wherein the adaptive reference voltage circuit comprises a diode-connected MOS transistor connected to the second reference voltage node.

11. The amplifier circuit of claim 9,

wherein during the first portion of the input common-mode adaptation phase, the fifth and sixth switches are activated to connect the second reference voltage node to the first and second output nodes of the input common-mode voltage adaptation circuit and apply the adaptive reference voltage to both the first and second differential input terminals of the differential amplifier stage, and the first and second switches are activated to connect the first and second feedback nodes to the first reference voltage node, and pre-charge the first and second capacitors to a voltage equal to the common-mode reference voltage less the adaptive reference voltage;

wherein during the second portion of the input common-mode adaptation phase, the first, second, fifth and sixth switches are deactivated, and the third and fourth switches are activated to capacitively couple the first differential output terminal to the first differential input terminal of the differential amplifier stage via the second capacitor, and to capacitively couple the second differential output terminal to the second differential input terminal of the differential amplifier stage via the first capacitor, and

wherein during a normal operating period of the amplifier circuit following the adaption phase, the first, second, third, fourth, fifth and sixth switches are deactivated, and the first input node of the amplifier circuit is capacitively coupled to the second differential input terminal of the differential amplifier stage via the first and third capacitors, and the second input node of the amplifier circuit is capacitively coupled to the first differential input terminal of the differential amplifier stage via the second and fourth capacitors.

12. The amplifier circuit of claim 5, further comprising an output common-mode feedback control circuit connected to the first and second differential output terminals of the differential amplifier stage, wherein the output common-mode feedback control circuit maintains an output common-mode voltage of the first and second differential output terminals of the differential amplifier stage at a common-mode reference voltage.

13. The amplifier circuit of claim 12, wherein the output common-mode feedback control circuit comprises:

first and, second input nodes connected to the first and second differential output terminals of the differential amplifier stage;

a reference voltage node that receives the common-mode reference voltage, and

an output node connected to a gate terminal of a tail transistor of the differential amplifier stage,

wherein during a control phase, the output common-mode feedback control circuit is configured to (i) connect the first and second differential output terminals of the differential amplifier stage to the gate terminal of the tail transistor to temporarily configure the tail transistor as a diode-connected transistor, wherein a voltage on the gate terminal of the tail device is adjusted to be equal to a diode voltage of the tail transistor, and to (ii) pre-charge a first and second capacitor to a voltage equal to the common-mode reference voltage less the diode voltage.

14. A system-on-chip comprising the amplifier circuit of claim 5.

15. The system-on-chip of claim 14, wherein the system-on-chip controls a storage system for storing data to and from a storage medium.

16. An amplifier circuit, comprising:

a differential amplifier comprising a differential transistor pair and a tail transistor connected to the differential transistor pair, the differential transistor pair comprising first and second differential input terminals and first and second differential output terminals; and

an output common-mode feedback control circuit comprising;

first and second input nodes connected to the first and second differential output terminals of the differential transistor pair,

a reference voltage node that receives a common-mode reference voltage, and

an output node connected to a gate terminal of the tail transistor of the differential amplifier,

wherein the output common-mode feedback control circuit maintains an output common-mode voltage of the first and second differential output terminals of the differential amplifier at a level of the common-mode reference voltage,

wherein during a control phase, the output common-mode feedback control circuit is configured to (i) connect the first and second differential output terminals of the differential amplifier stage to the gate terminal of the tail transistor to temporarily configure the tail transistor as a diode-connected transistor, wherein a voltage on the gate terminal of the tail device is adjusted to be equal to a diode voltage of the tail transistor, and to (ii) pre-charge a first and second capacitor to a voltage equal to the common-mode reference voltage less the diode voltage.

17. The amplifier circuit of claim 16, wherein the output common-mode feedback control circuit comprises:

a first switch connected between the reference voltage node and a first feedback node;

a second switch connected between the reference voltage node and a second feedback node;

a third switch connected between the first feedback node and the first differential output terminal;

a fourth switch connected between the second feedback node and the second differential output terminal;

a fifth switch connected between the first differential output terminal and the output node of the output common-mode feedback control circuit; and

a fifth switch connected between the second differential output terminal and the output node of the output common-mode feedback control circuit,

wherein the first capacitor is connected between the first feedback node and the output node, and

wherein the second capacitor is connected between the second feedback node and the output node.

18. The amplifier circuit of claim 17,

wherein during the control phase, the fifth and sixth switches are activated by a first control signal to directly connect the first and second differential output terminals of the differential transistor pair to the gate terminal of the tail transistor, and the first and second switches are activated by the first control signal to connect the reference voltage node to the first and second capacitors to precharge the first and second capacitors;

and

wherein during a normal operating period of the amplifier circuit, the first, second, fifth and sixth switches are deactivated, and the third and fourth switches are activated by a second control signal to capacitively couple the first differential output terminal of the differential transistor pair to the gate terminal of the tail transistor via the first capacitor, and to capacitively couple the second differential output terminal of the differential transistor pair to the gate terminal of the tail transistor via the second capacitor.

19. A system-on-chip comprising the amplifier circuit of claim 16.

20. The system-on-chip of claim 19, wherein the system-on-chip controls a storage system for storing data to and from a storage medium.