CHIP STACKING STRUCTURE

• US 20140177189A1
• Filed: 06/07/2013
• Published: 06/26/2014
• Est. Priority Date: 12/25/2012
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Liu, Chang-Chih, Wu, Shih-Hsien, Yu, Hsun, Chen, Peng-Shu
• Granted Patent: US 9,013,892 B2
• Time in Patent Office: Days
• US Class Current: 361/760
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/0239 Material of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/17106 the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/17515 Bump connectors having different functions
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48101 : Connecting bonding areas at the same height, e.g. horizontal bond
• CPC Class Codes: H01L 2224/4813 : Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 2224/48137 : the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/4917 : Crossed wires
• CPC Class Codes: H01L 2224/49175 : Parallel arrangements
• CPC Class Codes: H01L 2224/49177 : Combinations of different arrangements
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/64 : Impedance arrangements
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/00 : Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A chip stacking structure including a plurality of microbump structures, a plurality of first substrates, at least one first space layer, a plurality of second substrates and at least one second space layer is provided. The first substrates are stacked upon each other by a portion of the microbump structures, and each of the first substrates includes at least one first redistribution layer. The first space layer is located between the stacked first substrates. The second substrates are stacked on at least one of the first substrates by another portion of the microbump structures, and each of the second substrates includes at least one second redistribution layer. The second space layer is located between the stacked first and second substrates. The first redistribution layers, the second redistribution layers and the microbump structures form a plurality of impedance elements, and the impedance elements provide a specific oscillation frequency.

Claims

1. A chip stacking structure, comprising:

a plurality of microbump structures;

a plurality of first substrates, stacked upon each other by a first part of the microbump structures, and each of the first substrates comprises at least one first redistribution layer;

at least one first space layer, located between the first substrates, wherein the first part of the microbump structures is disposed in the at least one first space layer, and is configured to connect the at least one first redistribution layer of the first substrates;

a plurality of second substrates, stacked on at least one of the first substrates by a second part of the microbump structures, and each of the second substrates comprises at least one second redistribution layer; and

at least one second space layer, located between the first substrates and the second substrates, wherein the second part of the microbump structures is disposed in the at least one second space layer, and is configured to connect the at least one first redistribution layer of the first substrates and the at least one second redistribution layer of the second substrates,

wherein the first redistribution layers, the second redistribution layers and the microbump structures form a plurality of impedance elements, and the impedance elements provide a specific oscillation frequency.

2. The chip stacking structure according to claim 1, wherein the first substrates comprise:

a third substrate, having a first surface and a second surface opposite to each other, wherein the first redistribution layer of the third substrate is disposed on the first surface of the third substrate; and

a fourth substrate, stacked on the third substrate by the first part of the microbump structures, and having a third surface and a fourth surface opposite to each other, wherein the first redistribution layers of the fourth substrate are respectively disposed on the third surface and the fourth surface of the fourth substrate,

wherein the first redistribution layer disposed on the fourth surface of the fourth substrate and the first redistribution layer disposed on the first surface of the third substrate form at least one first impedance element of the impedance elements by the first part of the microbump structures.

3. The chip stacking structure according to claim 2, wherein the first impedance elements are connected in series or in parallel by a first conductive trace on the first redistribution layer of the fourth surface of the fourth substrate or a second conductive trace on the first redistribution layer of the first surface of the third substrate.

4. The chip stacking structure according to claim 2, wherein the first redistribution layer disposed on the third surface of the fourth substrate is connected to the first redistribution layer disposed on the fourth surface of the fourth substrate by at least one conductive via penetrating through the fourth substrate.

5. The chip stacking structure according to claim 2, wherein the second substrates comprise:

a fifth substrate, stacked on the fourth substrate by the second part of the microbump structures, and having a fifth surface and a sixth surface opposite to each other, wherein the second redistribution layer of the fifth substrate is disposed on the sixth surface of the fifth substrate; and

a sixth substrate, stacked on the fourth substrate by the second part of the microbump structures, and having a seventh surface and an eighth surface opposite to each other, wherein the second redistribution layer of the sixth substrate is disposed on the eighth surface of the sixth substrate,

wherein the second redistribution layer disposed on the sixth surface of the fifth substrate and the first redistribution layer disposed on the third surface of the fourth substrate form at least one second impedance element of the impedance elements by the second part of the microbump structures, and

wherein the second redistribution layer disposed on the eighth surface of the sixth substrate and the first redistribution layer disposed on the third surface of the fourth substrate form at least one third impedance element of the impedance elements by the second part of the microbump structures.

6. The chip stacking structure according to claim 5, wherein the at least one second impedance element is connected in series or in parallel to the at least one first impedance element by at least one conductive via penetrating through the fourth substrate.

7. The chip stacking structure according to claim 5, wherein the at least one third impedance element is connected in series or in parallel to the at least one first impedance element by at least one conductive via penetrating through the fourth substrate.

8. The chip stacking structure according to claim 5, wherein the at least one second impedance element and the at least one third impedance element are connected in series or in parallel by at least one conductive via penetrating through the fourth substrate, and a first conductive trace on the first redistribution layer of the fourth surface of the fourth substrate or a second conductive trace on the first redistribution layer of the first surface of the third substrate.

9. The chip stacking structure according to claim 2, wherein the second substrates comprise:

a seventh substrate, stacked on the fourth substrate by the second part of the microbump structures, and having a ninth surface and a tenth surface opposite to each other, wherein the second redistribution layers of the seventh substrate are respectively disposed on the ninth surface and the tenth surface of the seventh substrate; and

an eighth substrate, stacked on the fourth substrate by the second part of the microbump structures, and having a eleventh surface and a twelfth surface opposite to each other, wherein the second redistribution layers of the eighth substrate are respectively disposed on the eleventh surface and the twelfth surface of the eighth substrate,

wherein the second redistribution layer disposed on the tenth surface of the seventh substrate and the first redistribution layer disposed on the third surface of the fourth substrate form at least one fifth impedance element of the impedance elements by the second part of the microbump structures, and

wherein the second redistribution layer disposed on the twelfth surface of the eighth substrate and the first redistribution layer disposed on the third surface of the fourth substrate form at least one sixth impedance element of the impedance elements by the second part of the microbump structures.

10. The chip stacking structure according to claim 9, wherein the at least one fifth impedance element is connected in series or in parallel to the at least one first impedance element by at least one conductive via penetrating through the fourth substrate.

11. The chip stacking structure according to claim 9, wherein the at least one sixth impedance element is connected in series or in parallel to the at least one first impedance element by at least one conductive via penetrating through the fourth substrate.

12. The chip stacking structure according to claim 9, further comprising:

a plurality of wire bonding structures, connected to the second redistribution layer of the ninth surface of the seventh substrate and the second redistribution layer of the eleventh surface of the eighth substrate.

13. The chip stacking structure according to claim 12, wherein the second redistribution layer disposed on the ninth surface of the seventh substrate is connected to the second redistribution layer disposed on the tenth surface of the seventh substrate by at least one conductive via penetrating through the seventh substrate, and the second redistribution layer disposed on the eleventh surface of the eighth substrate is connected to the second redistribution layer disposed on the twelfth surface of the eighth substrate by the at least one conductive via penetrating through the eighth substrate.

14. The chip stacking structure according to claim 13, wherein the wire bonding structures, the second redistribution layers of the seventh substrate and the eighth substrate, the conductive vias penetrating through the seventh substrate and the eighth substrate, and the second part of the microbump structures connecting to the fourth substrate, the seventh substrate and the eighth substrate form at least one seventh impedance element of the impedance elements.

15. The chip stacking structure according to claim 14, wherein a material with high dielectric constant is further comprised between the seventh substrate and the eighth substrate, so as to enhance a capacitance of the at least one seventh impedance element.

16. The chip stacking structure according to claim 13, wherein the wire bonding structures, a conductive trace on the first redistribution layer of the third surface of the fourth substrate, the second redistribution layers of the seventh substrate and the eighth substrate, the conductive vias penetrating through the seventh substrate and the eighth substrate, and the second part of the microbump structures connecting to the fourth substrate, the seventh substrate and the eighth substrate form at least one eighth impedance element of the impedance elements.

17. The chip stacking structure according to claim 16, wherein a material with high permeability is further comprised between the seventh substrate and the eighth substrate, so as to enhance an inductance of the at least one eighth impedance element.