NON-VOLATILE MEMORY SYSTEM WITH RESET VERIFICATION MECHANISM AND METHOD OF OPERATION THEREOF
First Claim
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1. A method of operation of a non-volatile memory system comprising:
- providing a resistive storage element having a high resistance state and a low resistance state;
coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and
switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state.
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Abstract
A method of operation of a non-volatile memory system includes: providing a resistive storage element having a high resistance state and a low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state.
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Citations
20 Claims
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1. A method of operation of a non-volatile memory system comprising:
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providing a resistive storage element having a high resistance state and a low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state. - View Dependent Claims (2, 3, 4, 5)
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6. A method of operation of a non-volatile memory system comprising:
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providing a resistive storage element having a high resistance state and a low resistance state including forming conductive threads in the low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage including coupling a bit line and control bus for applying the bias voltage; and switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state including activating a read reference generator for establishing the verification bias to be ten times the voltage of the read bias. - View Dependent Claims (7, 8, 9, 10)
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11. A non-volatile memory system comprising:
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a resistive storage element having a high resistance state and a low resistance state; an analog multiplexer, coupled to the resistive storage element, for applying a bias voltage; and a read reference generator provides a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification