NON-VOLATILE MEMORY SYSTEM WITH RESET VERIFICATION MECHANISM AND METHOD OF OPERATION THEREOF

• US 20140177316A1
• Filed: 12/21/2012
• Published: 06/26/2014
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Sony Semiconductor Solutions Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Otsuka, Wataru, Sumino, Jun, Tsushima, Tomohito, Kitagawa, Makoto, Kunihiro, Takafumi
• Granted Patent: US 9,070,441 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/8416 adapted for supplying ionic species
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A method of operation of a non-volatile memory system includes: providing a resistive storage element having a high resistance state and a low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state.

Claims

1. A method of operation of a non-volatile memory system comprising:

providing a resistive storage element having a high resistance state and a low resistance state;

coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and

switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state.

2. The method as claimed in claim 1 further comprising accessing a sense amplifier coupled to analog multiplexer for monitoring a resistance.

3. The method as claimed in claim 1 wherein applying the bias voltage includes monitoring a high resistance verification threshold.

4. The method as claimed in claim 1 further comprising activating a plate voltage driver for establishing a reference voltage for the resistive storage element.

5. The method as claimed in claim 1 further comprising coupling a control field effect transistor for selecting the resistive storage element.

6. A method of operation of a non-volatile memory system comprising:

providing a resistive storage element having a high resistance state and a low resistance state including forming conductive threads in the low resistance state;

coupling an analog multiplexer to the resistive storage element for applying a bias voltage including coupling a bit line and control bus for applying the bias voltage; and

switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state including activating a read reference generator for establishing the verification bias to be ten times the voltage of the read bias.

7. The method as claimed in claim 6 further comprising accessing a sense amplifier coupled to analog multiplexer for monitoring a resistance of the resistive storage element including comparing a high resistance verification threshold against the resistance.

8. The method as claimed in claim 6 wherein applying the bias voltage includes monitoring a high resistance verification threshold including activating a word line driver for selecting the resistive storage element to compare against the high resistance verification threshold.

9. The method as claimed in claim 6 further comprising activating a plate voltage driver for establishing a reference voltage for the resistive storage element including coupling a second electrode of the resistive storage element to the reference voltage and coupling the first electrode of the resistive storage element to the bias voltage.

10. The method as claimed in claim 6 further comprising coupling a control field effect transistor for selecting the resistive storage element including activating a word line driver and a bit line and control bus for addressing a specific instance of the resistive storage element.

11. A non-volatile memory system comprising:

a resistive storage element having a high resistance state and a low resistance state;

an analog multiplexer, coupled to the resistive storage element, for applying a bias voltage; and

a read reference generator provides a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state.

12. The system as claimed in claim 11 further comprising a sense amplifier, coupled to analog multiplexer, for monitoring a resistance of the resistive storage element.

13. The system as claimed in claim 11 wherein the bias voltage applied provides a high resistance verification threshold compared to the resistance of the resistive storage element.

14. The system as claimed in claim 11 further comprising a plate voltage driver activated for establishing a reference voltage for the resistive storage element.

15. The system as claimed in claim 11 further comprising a control field effect transistor for selecting the resistive storage element.

16. The system as claimed in claim 11 further comprising:

conductive threads formed in the resistive storage element provides low resistance state;

a bit line and control bus for applying the bias voltage to the resistive storage element; and

a read reference generator sets the verification bias to be ten times the voltage of the read bias.

17. The system as claimed in claim 16 further comprising a sense amplifier, coupled to analog multiplexer, for monitoring a resistance of the resistive storage element includes a high resistance verification threshold compared against the resistance.

18. The system as claimed in claim 16 wherein the bias voltage applied to the resistive storage element provides a high resistance verification threshold and the resistive storage element, selected by a word line driver, is compared against the high resistance verification threshold.

19. The system as claimed in claim 16 further comprising a plate voltage driver establishes a voltage reference for the resistive storage element includes a second electrode of the resistive storage element coupled to the voltage reference and a first electrode of the resistive storage element coupled to the bias voltage.

20. The system as claimed in claim 16 further comprising a control field effect transistor for selecting the resistive storage element activated includes a word line driver and a bit line and control bus for addressing a specific instance of the resistive storage element.