SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

• US 20140177331A1
• Filed: 12/04/2013
• Published: 06/26/2014
• Est. Priority Date: 12/24/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: LEE, Hyun Jin
• Granted Patent: US 9,070,577 B2
• Time in Patent Office: Days
• US Class Current: 365/182
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/056 the transistor being a FinFET

Abstract

In order to fabricate a semiconductor device, a semiconductor substrate in a peripheral region is etched to form a plurality of holes. A gap-filling material is buried in the holes of the semiconductor substrate in the peripheral region, and first and second device isolation films are formed in the semiconductor device. A fin structure is formed by recessing the gap-filling material, and a gate is formed over a surface including the fin structure. As a result, operation characteristics of transistors formed in the peripheral region are improved and the short channel effects are also reduced.

Claims

1. A semiconductor device comprising:

a semiconductor substrate including a peripheral region;

an active region, a first device isolation region, and a second device isolation region formed in the semiconductor substrate of the peripheral region, the active region comprising a fin-type active region that corresponds to top and sidewall surfaces of the active region;

an insulation film formed in the first and second device isolation regions; and

a gate formed over the fin-type active region.

2. The semiconductor device according to claim 1, wherein the second device isolation region has a larger width than a first width of the first device isolation region, the first width of the first device isolation region being parallel to the width of the second device isolation region.

3. The semiconductor device according to claim 1, wherein the first device isolation region has an island shape.

4. The semiconductor device according to claim 1, wherein the insulation film in the first device isolation region is formed of a laminate structure of a sidewall oxide film and a liner insulation film, and wherein the liner insulation film comprises a nitride film.

5. The semiconductor device according to claim 1, wherein the insulation film in the second device isolation region is formed of a laminate structure of a sidewall oxide film, a liner insulation film, and a Spin On Dielectric (SOD) film, and wherein the liner insulation film comprises a nitride film.

6. The semiconductor device according to claim 1, wherein the gate is formed over the insulation film in the first device isolation region and the fin-type active region, and wherein the gate has a line shape.

7. The semiconductor device according to claim 1, further comprising:

a plurality of contact plugs formed near both sides of the gate outside the fin-type active region.

8. The semiconductor device according to claim 1, wherein a width of the gate is larger than a second width of the first device isolation region.

9. An electronic device comprising:

a memory device configured to store data and read the stored data in response to a data input/output (I/O) control signal; and

a memory controller configured to generate the data I/O control signal, and control data I/O operations of the memory device,

wherein the memory device includes;

a semiconductor substrate including a peripheral region;

an active region, a first device isolation region, and a second device isolation region formed in the semiconductor substrate of the peripheral region, the active region comprising a fin-type active region that corresponds to top and sidewall surfaces of the active region;

an insulation film formed in the first and second device isolation regions; and

a gate formed over the fin-type active region.

10. The electronic device according to claim 9, further comprising:

a processor configured to store data in the memory device by controlling the memory controller, and perform calculation corresponding to an external input command using data stored in the memory device.

11. The electronic device according to claim 10, wherein the memory controller and the processor are fabricated in a System on Chip (SoC) shape.

12. The electronic device according to claim 9, wherein the second device isolation region has a larger width than a first width of the first device isolation region, the first width of the first device isolation region being parallel to the width of the second device isolation region.

13. The electronic device according to claim 9, wherein the first device isolation region has an island shape.

14. The electronic device according to claim 9, wherein the insulation film in the first device isolation region is formed of a laminate structure of a sidewall oxide film and a liner insulation film, and wherein the liner insulation film comprises a nitride film.

15. The electronic device according to claim 9, wherein the insulation film in the second device isolation region is formed of a laminate structure of a sidewall oxide film, a liner insulation film, and a Spin On Dielectric (SOD) film, and wherein the liner insulation film comprises a nitride film.

16. The electronic device according to claim 9, wherein the gate is formed over the insulation film in the first device isolation region and the fin-type active region, and wherein the gate has a line shape.

17. The electronic device according to claim 9, further comprising:

a plurality of contact plugs formed near both sides of the gate outside the fin-type active region.

18. The electronic device according to claim 9, wherein a width of the gate is larger than a second width of the first device isolation region.