NON-VOLATILE MEMORY CELL

• US 20140177338A1
• Filed: 02/26/2014
• Published: 06/26/2014
• Est. Priority Date: 06/17/2010
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Ching, Wen-Hao, Wang, Shih-Chen
• Granted Patent: US 9,042,174 B2
• Time in Patent Office: Days
• US Class Current: 365/185.14
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A non-volatile memory cell comprises a coupling device, a first and a second select transistor, and a first and a second floating gate transistor is disclosed. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to the first floating gate transistor and the second select transistor. Moreover, the first select transistor, the first floating gate transistor, and the second select transistor are formed in a second conductivity region. The second floating gate transistor is formed in a third conductivity region, wherein the first conductivity region, the second conductivity region, and the third conductivity region are formed in a fourth conductivity region. The first conductivity region, the second conductivity region, and the third conductivity region are wells, and the fourth conductivity region is a deep well. The third conductivity region surrounds the first conductivity region and the second conductivity region.

Claims

1. A non-volatile memory cell comprising:

a coupling device formed in a first conductivity region;

a first select transistor serially connected to a first floating gate transistor and a second select transistor, wherein the first select transistor, the first floating gate transistor, and the second select transistor are formed in a second conductivity region; and

a second floating gate transistor formed in a third conductivity region, wherein the first conductivity region, the second conductivity region, and the third conductivity region are formed in a fourth conductivity region, and a gate of the first floating gate transistor, a gate of the second floating gate transistor, and an electrode of the coupling device are a single-polycrystalline formed floating gate;

wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells, and the fourth conductivity region is a deep well;

wherein the third conductivity region surrounds the first conductivity region and the second conductivity region.

2. The non-volatile memory cell of claim 1, wherein the first conductivity region and the second conductivity region are a first conductivity type, and the third conductivity region and the fourth conductivity region are a second conductivity type.

3. The non-volatile memory cell of claim 1, wherein the floating gate comprises:

a first gate part for forming the coupling device; and

a second gate part for forming the first floating gate transistor and the second floating gate transistor;

wherein the first gate part has a gate area larger than the second gate part.

4. The non-volatile memory cell of claim 1, wherein the coupling device is formed by a metal-oxide-semiconductor capacitor or a metal-oxide-semiconductor field effect transistor.

5. The non-volatile memory cell of claim 1, wherein the second floating gate transistor is formed by a metal-oxide-semiconductor field effect transistor or a metal-oxide-semiconductor capacitor.

6. The non-volatile memory cell of claim 1, wherein the first floating gate transistor is located between the first select transistor and the second select transistor.

7. The non-volatile memory cell of claim 6, further comprising:

a control line electrically connected to the coupling device;

a word line electrically connected to the gate of the first select transistor;

a select gate electrically connected to the gate of the second select transistor;

an erase line electrically connected to diffusion regions of the second floating gate transistor and the third conductivity region;

a bit line electrically connected to a drain region of the second select gate transistor; and

a source line electrically connected to a source region of the first select transistor.

8. The non-volatile memory cell of claim 7, wherein during a read operation, a control line voltage applied to the control line, a word line voltage applied to the word line, a select gate voltage applied to the select gate, an erase line voltage applied to the erase line, a bit line voltage applied to the bit line, a source line voltage applied to the source line, a first well voltage applied to the first conductivity region, a second well voltage applied to the second conductivity region, a third well voltage applied to the third conductivity region, and a fourth well voltage applied to the fourth conductivity region are configured for sensing current conducted through the serially-connected first select transistor, first floating gate transistor and second select transistor, wherein the first well voltage is equal to the control line voltage and the third well voltage is equal to the erase line voltage.

9. The non-volatile memory cell of claim 7, wherein during a program operation, a control line voltage applied to the control line, a word line voltage applied to the word line, a select gate voltage applied to the select gate, an erase line voltage applied to the erase line, a bit line voltage applied to the bit line, a source line voltage applied to the source line, a first well voltage applied to the first conductivity region, a second well voltage applied to the second conductivity region, a third well voltage applied to the third conductivity region, and a fourth well voltage applied to the fourth conductivity region are configured for inducing Fowler-Nordheim tunneling injection at the first floating gate transistor, wherein the first well voltage is equal to the control line voltage and the third well voltage is equal to the erase line voltage.

10. The non-volatile memory cell of claim 7, wherein during a program inhibit operation, a control line voltage applied to the control line, a word line voltage applied to the word line, a select gate voltage applied to the select gate, an erase line voltage applied to the erase line, a bit line voltage applied to the bit line, a source line voltage applied to the source line, a first well voltage applied to the first conductivity region, a second well voltage applied to the second conductivity region, a third well voltage applied to the third conductivity region, and a fourth well voltage applied to the fourth conductivity region are configured for forcing cut-off of the first and second select transistors, wherein the first well voltage is equal to the control line voltage and the third well voltage is equal to the erase line voltage.

11. The non-volatile memory cell of claim 7, wherein during an erase operation, a control line voltage applied to the control line, a word line voltage applied to the word line, a select gate voltage applied to the select gate, an erase line voltage applied to the erase line, a bit line voltage applied to the bit line, a source line voltage applied to the source line, a first well voltage applied to the first conductivity region, a second well voltage applied to the second conductivity region, a third well voltage applied to the third conductivity region, and a fourth well voltage applied to the fourth conductivity region are configured for inducing Fowler-Nordheim tunneling ejection at the second floating gate transistor, wherein the third well voltage is equal to the erase line voltage.

12. The non-volatile memory cell of claim 7, wherein rising edges of the third well voltage applied to the third conductivity region lead rising edges of the first well voltage applied to the first conductivity region and falling edges of the third well voltage applied to the third conductivity region lag falling edges of the first well voltage applied to the first conductivity region.