NON-VOLATILE REGISTER AND NON-VOLATILE SHIFT REGISTER

• US 20140177348A1
• Filed: 12/21/2012
• Published: 06/26/2014
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Synerger Incorporated
• Original Assignee: Flashsilicon, Incorporation
• Inventors: WANG, Lee
• Granted Patent: US 9,117,518 B2
• Time in Patent Office: Days
• US Class Current: 365/189.05
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

Non-Volatile Register (NVR) and Non-Volatile Shift Register (NVSR) devices are disclosed. The innovative NVR and NVSR devices of the invention can rapidly load the stored non-volatile data in non-volatile memory elements into their correspondent static memory elements for fast and constant referencing in digital circuitry. According to the invention, the loading process from non-volatile memory to static memory is a direct process without going through the conventional procedures of accessing the non-volatile memory, sensing from the non-volatile memory, and loading into the digital registers and shift registers.

Claims

1. An non-volatile register cell, comprising:

a static memory element having a first output node and a second output node;

a non-volatile memory (NVM) element having a charge storing material, a control gate electrode, a first source/drain electrode and a second source/drain electrode, the first source/drain electrode being coupled to the first output node; and

a reset transistor coupled to the second output node.

2. The non-volatile register cell according to claim 1, wherein when the reset transistor is N-type, the reset transistor is coupled between the second output node and a ground node carrying a ground voltage, otherwise the reset transistor is coupled between the second output node and an operating node carrying an operating voltage.

3. The non-volatile register cell according to claim 2, wherein the second output node is reset to a predetermined voltage when a gate voltage is applied to a gate electrode of the reset transistor.

4. The non-volatile register cell according to claim 3, wherein when the reset transistor is N-type, the gate voltage is the operating voltage and the predetermined voltage is the ground voltage, and wherein when the reset transistor is P-type, the gate voltage is the ground voltage and the predetermined voltage is the operating voltage.

5. The non-volatile register cell according to claim 1, wherein when the NVM element is N-type, a control gate voltage is applied to the control gate electrode and the second source/drain electrode is coupled to a ground node carrying a ground voltage to load an non-volatile value from the NVM element into the static memory element, and wherein the control gate voltage is between a programmed threshold voltage and an erased threshold voltage of the NVM element.

6. The non-volatile register cell according to claim 1, wherein when the NVM element is P-type, an operating node carrying an operating voltage is coupled to the control gate electrode, the second source/drain electrode and a well electrode of the NVM element to load an non-volatile value from the NVM element into the static memory element.

7. The non-volatile register cell according to claim 1, wherein after the second output node is reset and then an non-volatile value is loaded from the NVM element into the static memory element, the second output node has the ground voltage if the NVM element is in a programmed threshold voltage state and the second output node has the operating voltage if the NVM element is in an erased threshold voltage state.

8. The non-volatile register cell according to claim 1, wherein the static memory element comprises a latch.

9. An non-volatile shift register cell, comprising:

a latch having at least an input node, a first output node and a second output node, the input node and the first output node being complementary to each other;

a non-volatile memory (NVM) element having a charge storing material, a control gate electrode, a first source/drain electrode and a second source/drain electrode, the first source/drain electrode being coupled to the first output node;

a reset transistor coupled to the second output node; and

a first switch and a second switch connected in series at an intermediate node and controlled by a clock signal, the intermediate node being coupled to the input node, an output terminal of the two switches being coupled to the second output node.

10. The non-volatile shift register cell according to claim 9, wherein the first switch is enabled to pass an input voltage at an input terminal of the two switches to the intermediate node and the second switch is disabled in response to a first state of the clock signal, and wherein the second switch is enabled to connect the intermediate node to the second output node and the first switch is disabled in response to a second state of the clock signal.

11. The non-volatile shift register cell according to claim 10, wherein when the first switch is enabled and the second switch is disabled, the second output node generates the input voltage, and wherein when the first switch is disabled and the second switch is enabled, the input voltage is isolated from the latch.

12. The non-volatile shift register cell according to claim 9, wherein when the reset transistor is N-type, the reset transistor is coupled between the second output node and a ground node carrying a ground voltage, otherwise the reset transistor is coupled between the second output node and an operating node carrying an operating voltage.

13. The non-volatile shift register cell according to claim 12, wherein the second output node is reset to a predetermined voltage when a gate voltage is applied to a gate electrode of the reset transistor.

14. The non-volatile shift register cell according to claim 13, wherein when the reset transistor is N-type, the gate voltage is the operating voltage and the predetermined voltage is the ground voltage, and wherein when the reset transistor is P-type, the gate voltage is the ground voltage and the predetermined voltage is the operating voltage.

15. The non-volatile shift register cell according to claim 9, wherein when the NVM element is N-type, a control gate voltage is applied to the control gate electrode and the second source/drain electrode is coupled to a ground node carrying a ground voltage to load an non-volatile value from the NVM element into the latch, and wherein the control gate voltage is between a programmed threshold voltage and an erased threshold voltage of the NVM element.

16. The non-volatile shift register cell according to claim 9, wherein when the NVM element is P-type, an operating node carrying an operating voltage is coupled to the control gate electrode, the second source/drain electrode and a well electrode of the NVM element to load an non-volatile value from the NVM element into the latch.

17. The non-volatile shift register cell according to claim 9, wherein after the second output node is reset and then an non-volatile value is loaded from the NVM element into the latch, the second output node has the ground voltage if the NVM element is in a programmed threshold voltage state and the second output node has the operating voltage if the NVM element is in an erased threshold voltage state.

18. An operating method for a non-volatile register cell having a static memory element, a non-volatile memory (NVM) element and a reset transistor, the static memory element having a first output node and a second output node, one of two source/drain electrodes of the NVM element being coupled to the first output node, the reset transistor coupled to the second output node, the operating method comprising the sequential steps of:

resetting the second output node to a predetermined voltage by the reset transistor;

when the NVM element is N-type, loading an non-volatile value from the NVM element into the static memory element by applying a control gate voltage to a control gate of the NVM element and applying a ground voltage to the other source/drain electrode of the NVM element; and

when the NVM element is P-type, loading the non-volatile value from the non-volatile memory (NVM) element into the static memory element by applying an operating voltage to the control gate, the other source/drain electrode and a well electrode of the NVM element;

wherein the control gate voltage is between an erased threshold voltage and a programmed threshold voltage of the NVM element.

19. The method according to claim 18, wherein the step of resetting comprises:

when the reset transistor is N-type, applying the operating voltage to a gate of the reset transistor to reset the second output node to the ground voltage; and

when the reset transistor is P-type, applying the ground voltage to the gate of the reset transistor to reset the second output node to the operating voltage.

20. The method according to claim 18, wherein the NVM element is N-type, and wherein when the NVM element is in a programmed threshold voltage state, the NVM element is turned off, otherwise the NVM element is turned on during the step of loading the non-volatile value from the NVM element into the static memory element.

21. The method according to claim 18, wherein the NVM element is P-type, and wherein when the NVM element is in a programmed threshold voltage state, the NVM element is turned on, otherwise the NVM element is turned off during the step of loading the non-volatile value from the NVM element into the static memory element.

22. The method according to claim 18, further comprising:

when the NVM element is in a programmed threshold voltage state, causing the second output node to have the ground voltage, otherwise causing the second output node to have the operating voltage after the step of loading the non-volatile value from the NVM element into the static memory element.

23. An operating method for a non-volatile shift register cell having a non-volatile memory (NVM) element, a latch, a reset transistor, a first switch and a second switch, the latch having at least an input node, a first output node and a second output node, the input node and the first output node being complementary to each other, one of two source/drain electrodes of the NVM element being coupled to the first output node, the first switch and the second switch being connected in series at an intermediate node, the reset transistor and an output terminal of the two switches being coupled to the second output node, the intermediate node being coupled to the input node, the operating method comprising:

resetting the second output node to a predetermined voltage by the reset transistor;

when the NVM element is N-type, loading an non-volatile value from the NVM element into the latch by applying a control gate voltage to a control gate of the NVM element and applying a ground voltage to the other source/drain electrode of the NVM element;

when the NVM element is P-type, loading the non-volatile value from the NVM element into the latch by applying an operating voltage to the control gate, the other source/drain electrode and a well electrode of the NVM element;

passing an input voltage at an input terminal of the two switches to the intermediate node by the two switches according to a clock signal; and

coupling the intermediate node to the second output node by the two switches according to the clock signal;

wherein the control gate voltage is between an erased threshold voltage and a programmed threshold voltage of the NVM element.

24. The method according to claim 23, wherein the step of passing the input voltage comprises:

enabling the first switch to pass the input voltage to the intermediate node according to a first state of the clock signal; and

disabling the second switch according to the first state of a clock signal.

25. The method according to claim 24, further comprising:

causing the second output node to have the input voltage by the latch after the step of passing the input voltage.

26. The method according to claim 23, wherein the step of coupling comprises:

disabling the first switch according to a second state of the clock signal; and

enabling the second switch to couple the intermediate node to the second output node according to the second state of the clock signal.

27. The method according to claim 23, wherein the step of resetting comprises:

when the reset transistor is N-type, applying the operating voltage to a gate of the reset transistor to reset the second output node to the ground voltage; and

when the reset transistor is P-type, applying the ground voltage to the gate of the reset transistor to reset the second output node to the operating voltage.

28. The method according to claim 23, wherein the NVM element is N-type, and wherein when the NVM element is in a programmed threshold voltage state, the NVM element is turned off, otherwise the NVM element is turned on during the step of loading the non-volatile value from the NVM element into the latch.

29. The method according to claim 23, wherein the NVM element is P-type, and wherein when the NVM element is in a programmed threshold voltage state, the NVM element is turned on, otherwise the NVM element is turned off during the step of loading the non-volatile value from the NVM element into the latch.

30. The method according to claim 23, further comprising:

when the NVM element is in a programmed threshold voltage state, causing the second output node to have the ground voltage, otherwise causing the second output node to have the operating voltage after the step of loading the non-volatile value from the NVM element into the latch and prior to the steps of passing and coupling.