NON-VOLATILE REGISTER AND NON-VOLATILE SHIFT REGISTER
First Claim
Patent Images
1. An non-volatile register cell, comprising:
- a static memory element having a first output node and a second output node;
a non-volatile memory (NVM) element having a charge storing material, a control gate electrode, a first source/drain electrode and a second source/drain electrode, the first source/drain electrode being coupled to the first output node; and
a reset transistor coupled to the second output node.
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Abstract
Non-Volatile Register (NVR) and Non-Volatile Shift Register (NVSR) devices are disclosed. The innovative NVR and NVSR devices of the invention can rapidly load the stored non-volatile data in non-volatile memory elements into their correspondent static memory elements for fast and constant referencing in digital circuitry. According to the invention, the loading process from non-volatile memory to static memory is a direct process without going through the conventional procedures of accessing the non-volatile memory, sensing from the non-volatile memory, and loading into the digital registers and shift registers.
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Citations
30 Claims
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1. An non-volatile register cell, comprising:
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a static memory element having a first output node and a second output node; a non-volatile memory (NVM) element having a charge storing material, a control gate electrode, a first source/drain electrode and a second source/drain electrode, the first source/drain electrode being coupled to the first output node; and a reset transistor coupled to the second output node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An non-volatile shift register cell, comprising:
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a latch having at least an input node, a first output node and a second output node, the input node and the first output node being complementary to each other; a non-volatile memory (NVM) element having a charge storing material, a control gate electrode, a first source/drain electrode and a second source/drain electrode, the first source/drain electrode being coupled to the first output node; a reset transistor coupled to the second output node; and a first switch and a second switch connected in series at an intermediate node and controlled by a clock signal, the intermediate node being coupled to the input node, an output terminal of the two switches being coupled to the second output node. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. An operating method for a non-volatile register cell having a static memory element, a non-volatile memory (NVM) element and a reset transistor, the static memory element having a first output node and a second output node, one of two source/drain electrodes of the NVM element being coupled to the first output node, the reset transistor coupled to the second output node, the operating method comprising the sequential steps of:
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resetting the second output node to a predetermined voltage by the reset transistor; when the NVM element is N-type, loading an non-volatile value from the NVM element into the static memory element by applying a control gate voltage to a control gate of the NVM element and applying a ground voltage to the other source/drain electrode of the NVM element; and when the NVM element is P-type, loading the non-volatile value from the non-volatile memory (NVM) element into the static memory element by applying an operating voltage to the control gate, the other source/drain electrode and a well electrode of the NVM element; wherein the control gate voltage is between an erased threshold voltage and a programmed threshold voltage of the NVM element. - View Dependent Claims (19, 20, 21, 22)
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23. An operating method for a non-volatile shift register cell having a non-volatile memory (NVM) element, a latch, a reset transistor, a first switch and a second switch, the latch having at least an input node, a first output node and a second output node, the input node and the first output node being complementary to each other, one of two source/drain electrodes of the NVM element being coupled to the first output node, the first switch and the second switch being connected in series at an intermediate node, the reset transistor and an output terminal of the two switches being coupled to the second output node, the intermediate node being coupled to the input node, the operating method comprising:
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resetting the second output node to a predetermined voltage by the reset transistor; when the NVM element is N-type, loading an non-volatile value from the NVM element into the latch by applying a control gate voltage to a control gate of the NVM element and applying a ground voltage to the other source/drain electrode of the NVM element; when the NVM element is P-type, loading the non-volatile value from the NVM element into the latch by applying an operating voltage to the control gate, the other source/drain electrode and a well electrode of the NVM element; passing an input voltage at an input terminal of the two switches to the intermediate node by the two switches according to a clock signal; and coupling the intermediate node to the second output node by the two switches according to the clock signal; wherein the control gate voltage is between an erased threshold voltage and a programmed threshold voltage of the NVM element. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30)
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Specification