Memory Interface Supporting Both ECC and Per-Byte Data Masking

• US 20140177362A1
• Filed: 12/20/2012
• Published: 06/26/2014
• Est. Priority Date: 12/20/2012
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: O'CONNOR, James, Kruger, Warren
• Granted Patent: US 9,064,606 B2
• Time in Patent Office: Days
• US Class Current: 365/201
• CPC Class Codes: G06F 11/1052 Bypassing or disabling error detection or correction
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1009 Data masking during input/output

Abstract

A memory and a method of storing data in a memory are provided. The memory comprises a memory block comprising data bits and additional bits. The memory includes logic which, when receiving a first command, writes data into the data bits of the memory block, wherein the data is masked according to a first input. The logic, in response to a second command, writes data into the data bits of the memory block and writes a second input into the additional bits of the memory block.

Claims

1. A memory comprising:

a memory block comprising data bits and additional bits;

logic configured to,

responsive to a first command, write data into the data bits of the memory block, wherein the data is masked according to a first input; and

responsive to a second command, write data into the data bits of the memory block and write a second input into the additional bits of the memory block.

2. The memory of claim 1, wherein the memory further comprises a bus channel input configured to receive the first input and the second input.

3. The memory of claim 1, wherein the memory further comprises a first bus channel input configured to receive the first input and a second bus channel input configured to receive the second input.

4. The memory of claim 1, wherein the first command causes the logic to write “

don'"'"'t care”

values into the additional bits.

5. The memory of claim 1, wherein the first command causes the logic to write a per-byte parity bit into the additional bits.

6. The memory of claim 1, wherein the data is masked according to a per-byte bit mask.

7. The memory of claim 1, wherein responsive to a third command the data from the data bits and the additional bits is output by the logic.

8. The memory of claim 1, wherein the memory further comprises a mode bit, and wherein the first command comprises a write command when the mode bit is set to a first value, and wherein the second command comprises the write command when the mode bit set to a second value.

9. A method comprising:

transmitting, to a memory, a first command, wherein the first command causes the memory to write data into data bits of a memory block, wherein the data is masked according to a first input to the memory; and

transmitting, to a memory, a second command, wherein the second command causes the memory to write data into the data bits of the memory block and write a second input to the memory into additional bits of the memory block.

10. The method of claim 9, wherein transmitting the first command comprises transmitting the first command on a bus and wherein transmitting the second command comprises transmitting the second command on the bus.

11. The method of claim 9, wherein transmitting the first command comprises transmitting the first command on a first bus and wherein transmitting the second command comprises transmitting the second command on a second bus.

12. The method of claim 9, wherein the first command causes the memory to write “

don'"'"'t care”

values into the additional bits.

13. The method of claim 9, wherein the first command causes the memory to write a per-byte parity bit into the additional bits.

14. The method of claim 9, wherein the data is masked according to a per-byte bit mask.

15. The method of claim 9, wherein responsive to a third command the data from the data bits and the additional bits is output by the memory.

16. The method of claim 9, wherein the first command is issued responsive to an address of the data bits being in a first set of addresses, and wherein the second command is issued responsive to the address being in a second set of addresses.

17. The method of claim 9, wherein the first command is issued responsive to a determination that the memory does not support additional bits.

18. The method of claim 9, wherein the second command is issued responsive to a determination that the memory supports additional bits.

19. A method comprising:

receiving, by a memory, a first command, wherein the first command causes the memory to write data into data bits of a memory block, wherein the data is masked according to a first input to the memory; and

receiving, by the memory, a second command, wherein the second command causes the memory to write data into the data bits of the memory block and write a second input to the memory into additional bits of the memory block.

20. The method of claim 19, wherein receiving the first command comprises receiving the first command on a bus and wherein receiving the second command comprises receiving the second command on the bus.

21. The method of claim 19, wherein receiving the first command comprises receiving the first command on a first bus and wherein receiving the second command comprises receiving the second command on a second bus.

22. The method of claim 19, wherein the first command causes the memory to write “

don'"'"'t care”

values into the additional bits.

23. The method of claim 19, wherein the first command causes the memory to write a per-byte parity bit into the additional bits.

24. The method of claim 19, wherein the data is masked according to a per-byte bit mask.

25. The method of claim 19, wherein responsive to a third command the data from the data bits and the additional bits is output by the memory.