Frequency Based Feedback Control

• US 20140177890A1
• Filed: 01/14/2013
• Published: 06/26/2014
• Est. Priority Date: 12/20/2012
• Status: Active Grant

• Current Assignee: Cochlear Limited
• Original Assignee: Mats Hojlund
• Inventors: Hillbratt, Martin, Hjlund, Mats
• Granted Patent: US 9,351,085 B2
• Time in Patent Office: Days
• US Class Current: 381/318
• CPC Class Codes: G10L 21/0232 Processing in the frequency domain
• CPC Class Codes: H04R 25/353 Frequency, e.g. frequency shift or compression
• CPC Class Codes: H04R 25/453 electronically
• CPC Class Codes: H04R 25/505 using digital signal processing
• CPC Class Codes: H04R 25/606 acting directly on the eardrum, the ossicles or the skull, e.g. mastoid, tooth, maxillary or mandibular bone, or mechanically stimulating the cochlea, e.g. at the oval window

Abstract

Disclosed herein is a feedback reduction system for used in a hearing prosthesis. The hearing prosthesis will receive an input signal, process the input signal, and create a transformed output. However, the hearing prosthesis may suffer from feedback. Thus, a system to minimize the feedback in a hearing prosthesis may be desirable. One system to minimize the feedback includes down-sample circuitry configured to down-sample a first signal, creating a down-sampled signal. They system also includes a filter circuit. The filter circuit filters both the first signal and the down-sampled signal. The filter will output a filtered signal and a filtered down-sampled signal, respectively. Additionally, the system features up-sample circuitry that up-samples the filtered down-sampled signal. The output of the up-sample circuitry is an up-sampled signal. Further, the system features combining circuitry that creates a feedback-reduced signal based on the up-sampled signal, the filtered signal, and an input signal.

Claims

1. A signal processing system, the system comprising:

a filter with a fixed number of output taps;

first processing circuitry configured to provide one or the other of two signals, the signals including first and second signals, to an input of the filter, the first processing circuitry further configured to generate the first signal by altering the bandwidth of the second signal, wherein the second signal is an output of the signal processing system; and

combining circuitry configured to generate a processed signal from an input signal to the combining circuitry based on an output of the filter.

2. The signal processing system of claim 1, further comprising second processing circuitry, wherein the processed signal is an input to the second processing circuitry and an output of the second processing circuitry is the output of the signal processing system.

3. The signal processing system of claim 1, wherein the first processing circuitry comprises a down sampler, wherein the second signal is an input to the down sampler and the first signal is an output of the down sampler.

4. The signal processing system of claim 1, wherein the first processing circuitry comprises a down sampler and a buffer, wherein the second signal is an input to the down sampler, an output of the down sampler is an input to the buffer and the first signal is an output of the buffer.

5. The signal processing system of claim 3, wherein the first processing circuitry further comprises a switch, wherein the switch alternately couples the second signal or the first signal to the input of the filter.

6. The signal processing system of claim 1, further comprising an up sampler, wherein the output of the filter is an input to the up sampler.

7. The signal processing system of claim 6, further comprising a switch, wherein the switch alternately couples an output of the up sampler or the output of the filter to the combining circuitry.

8. The signal processing system of claim 1, further comprising an up sampler and a down sampler, wherein a sample factor of the up sampler is proportional to a sample factor of the down sampler.

9. The signal processing system of claim 1, wherein the filter circuit is configured to filter the first signal with a first time interval and further configured to filter the second signal with a second time interval and wherein the first and second time intervals are different.

10. The signal processing system of claim 1, wherein the combining circuitry is configured to reduce or eliminate feedback from the input signal based on the output of the filter.

11. A method of operating a signal processing system comprising a signal path, the method comprising:

down-sampling outside of the signal path a first signal from the signal path, creating a down-sampled signal;

filtering outside of the signal path the down-sampled signal, creating a filter down-sampled signal;

up-sampling outside of the signal path the filter down-sampled signal, creating an up-sampled signal; and

altering a second signal inside the signal path based on the up-sampled signal.

12. The method of claim 11, further comprising buffering the down-sampled signal prior to filtering the down-sampled signal.

13. The method of claim 11, further comprising processing a signal inside the signal path, creating the first signal.

14. The method of claim 11, further comprising, outside of the signal path, filtering a third signal from the signal path to create a set of processed data, wherein the full bandwidth of the third signal at least partially overlaps the full bandwidth of the down-sampled signal.

15. The method of claim 14, wherein the first signal is the third signal.

16. The method of claim 14, further comprising, altering a fourth signal inside the signal path by one or both of manipulating the third signal according to the set of processed data or combining the third signal with the set of processed data.

17. The method of claim 11, wherein the altering comprises altering the second signal inside the signal path by one or both of manipulating the second signal according to the up-sampled signal or combining the second signal with the up-sampled signal.

18. A signal processing system, the system comprising:

a first process circuit configured generate a first processed signal from an input to the first process circuit based on a first signal; and

a second process circuit configured generate a second processed signal from the first processed signal based on a second signal,

wherein the first signal is the first processed signal or an output of the signal processing system,

wherein the second signal is the second processed signal or the output of the signal processing system, and

wherein the first process circuit operates on a first frequency band, the second process circuit operates on a second frequency band, the first and second frequency bands are different, and the first and second frequency bands overlap.

19. The signal processing system of claim 18, further comprising processing circuitry, wherein the second processed signal is an input to the processing circuitry and an output of the processing circuitry is the output of the signal processing system.

20. The signal processing system of claim 18, wherein the first frequency band is narrower than the second frequency band.

21. The signal processing system of claim 20, wherein the second frequency band is the full bandwidth of the second processed signal or the output of the signal processing system.

22. The signal processing system of claim 18, wherein the first frequency band is limited to low frequency components of the first processed signal or the output of the signal processing system.

23. The signal processing system of claim 18, wherein the first process circuit comprises a first down sampler, a filter, an up sampler and a combiner.

24. The signal processing system of claim 23, wherein the first processed signal is an input to the first down sampler.

25. The signal processing system of claim 23, wherein the first process circuit further comprises a second down sampler, wherein the output of the signal processing system is an input to the second down sampler, an output of the second down sampler is an input to the filter, an output of the filter is an input to the up sampler, an output of the up sampler and the first signal are inputs to the combiner circuit, and the combiner outputs first the processed signal.