SELECTIVE CACHE MEMORY WRITE-BACK AND REPLACEMENT POLICIES

• US 20140181402A1
• Filed: 12/21/2012
• Published: 06/26/2014
• Est. Priority Date: 12/21/2012
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: WHITE, Sean T.
• Application Number:
  US13/724,343
• Publication Number:
  US 20140181402A1
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/127 using additional replacement algorithms

Abstract

A method of managing cache memory includes assigning a caching priority designator to an address that addresses information stored in a memory system. The information is stored in a cacheline of a first level of cache memory in the memory system. The cacheline is evicted from the first level of cache memory. A second level in the memory system to which to write back the information is determined based at least in part on the caching priority designator. The information is written back to the second level.

Claims

1. A method of managing cache memory, comprising:

assigning a caching priority designator to an address that addresses information stored in a memory system;

storing the information in a cacheline of a first level of cache memory in the memory system;

evicting the cacheline from the first level of cache memory;

determining a second level in the memory system to which to write back the information, based at least in part on the caching priority designator; and

writing back the information to the second level.

2. The method of claim 1, wherein:

the address is a virtual address; and

assigning the caching priority designator comprises storing the caching priority designator in a page translation table.

3. The method of claim 1, wherein:

the address is included within a range of addresses; and

assigning the caching priority designator comprises storing the caching priority designator in a field of a memory-type range register, wherein the field corresponds to the range of addresses.

4. The method of claim 1, wherein:

the memory system comprises main memory and multiple levels of cache memory; and

determining the second level comprises;

selecting a level of cache memory immediately above the first level of cache memory as the second level when the caching priority designator has a first value; and

selecting main memory as the second level when the caching priority designator has a second value.

5. The method of claim 4, wherein the first level of cache memory is selected from the group consisting of an L1 cache and an L2 cache.

6. The method of claim 1, further comprising selecting the cacheline for eviction based at least in part on the caching priority designator.

7. The method of claim 6, wherein:

the cacheline is a first cacheline of a set of cachelines;

the selecting is performed in accordance with a least-recently-used (LRU) policy; and

the method further comprises, before the selecting;

accessing respective cachelines of the set of cachelines;

specifying an accessed cacheline as most recently used when a corresponding caching priority designator has a first value; and

specifying an accessed cacheline as least recently used when a corresponding caching priority designator has a second value.

8. The method of claim 6, wherein:

the cacheline is a first cacheline of a set of cachelines;

the selecting is performed in accordance with bits indicating whether cachelines of the set have been accessed since previously being considered for eviction; and

the method further comprises, before the selecting;

accessing respective cachelines of the set of cachelines;

asserting a bit for an accessed cacheline when a corresponding caching priority designator has a first value; and

de-asserting a bit for an accessed cacheline when a corresponding caching priority designator has a second value.

9. The method of claim 1, further comprising:

monitoring addresses of requested information;

based on the monitoring, determining a predicted address, wherein the predicted address is assigned a corresponding caching priority designator;

verifying that the corresponding caching priority designator has a value that allows prefetching; and

in response to the verifying, prefetching information addressed by the predicted address into a specified level of cache memory.

10. The method of claim 1, wherein the caching priority designator comprises a first bit to indicate whether the information comprises data or instructions.

11. The method of claim 1, wherein the caching priority designator further comprises a second bit to indicate, for information that comprises data, a caching priority of the data.

12. A circuit, comprising:

multiple levels of cache memory, including a first level of cache memory;

an interconnect to couple to a main memory, wherein the main memory and the multiple levels of cache memory are to compose a plurality of levels of a memory system; and

a cache controller to evict a cacheline from the first level of cache memory and to determine a second level of the plurality of levels to which to write back information stored in the evicted cacheline based at least in part on a caching priority designator assigned to an address of the information.

13. The circuit of claim 12, further comprising a page translation table to assign the caching priority designator to the address.

14. The circuit of claim 12, further comprising a memory-type range register to assign the caching priority designator to a range of addresses that includes the address.

15. The circuit of claim 12, wherein:

the first level of cache memory is an L1 cache;

the multiple levels of cache memory further comprise an L2 cache; and

the cache controller is to determine the second level by selecting the L2 cache when the caching priority designator has a first value and selecting the main memory when the caching priority designator has a second value.

16. The circuit of claim 12, wherein:

the first level of cache memory is an L2 cache;

the multiple levels of cache memory further comprise an L1 cache and an L3 cache; and

the cache controller is to determine the second level by selecting the L3 cache when the caching priority designator has a first value and selecting the main memory when the caching priority designator has a second value.

17. The circuit of claim 12, wherein the cache controller comprises replacement logic to select the cacheline for eviction based at least in part on the caching priority designator.

18. The circuit of claim 12, further comprising a prefetcher to speculatively fetch blocks of information into a specified level of cache memory based at least in part on values of caching priority designators assigned to addresses of the blocks of information.

19. The circuit of claim 12, wherein the cache controller comprises a register to selectively enable or disable use of the caching priority designator.

20. A non-transitory computer-readable storage medium storing instructions, which when executed by one or more processor cores, cause the one or more processor cores to assign a caching priority designator to an address that addresses information stored in memory;

wherein a first level of cache memory, when evicting a cacheline storing the information, is to determine a second level of memory to which to write back the information based at least in part on the caching priority designator.