REDUCING POWER CONSUMPTION OF VOLATILE MEMORY VIA USE OF NON-VOLATILE MEMORY

• US 20140181558A1
• Filed: 12/22/2012
• Published: 06/26/2014
• Est. Priority Date: 12/22/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Taha, Ali, Gandhi, Vipul, Giddi, Phani Babu
• Granted Patent: US 9,891,694 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3212 Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method includes initiating a transition from an operating mode to a sleep mode at an electronic device that includes a volatile memory and a non-volatile memory. In response to the initiating, data is copied from the volatile memory to the non-volatile memory and a portion of the volatile memory is disabled. Another method includes determining that a low performance mode condition is satisfied at an electronic device that includes a volatile memory that stores a first copy of read-only data and a non-volatile memory that stores a second copy of the read-only data. A memory mapping of the read-only data is updated from the volatile memory to the non-volatile memory. A portion of the volatile memory that stores the first copy is disabled and access of the read-only data is directed to the non-volatile memory instead of the volatile memory.

Claims

1. A method comprising:

initiating a transition from an operating mode to a sleep mode at an electronic device, wherein the electronic device comprises a volatile memory device having a first size and a non-volatile memory device having a second size that is greater than or equal to the first size;

in response to the initiating, copying data from the volatile memory device to the non-volatile memory device; and

disabling a portion of the volatile memory device during the sleep mode.

2. The method of claim 1, wherein the data copied from the volatile memory device to the non-volatile memory device comprises a data image.

3. The method of claim 1, wherein the data is copied to a portion of the non-volatile memory device that is reserved for data transfers from the volatile memory device.

4. The method of claim 1, wherein disabling the portion of the volatile memory device comprises turning off power to the portion of the volatile memory device.

5. The method of claim 1, wherein the volatile memory device comprises a dynamic random access memory (DRAM).

6. The method of claim 5, wherein disabling the volatile memory device comprises disabling refreshing of the volatile memory device during the sleep mode.

7. The method of claim 5, wherein the DRAM comprises a double data rate (DDR) synchronous DRAM (SDRAM).

8. The method of claim 5, wherein the non-volatile memory device comprises NOR Flash memory, NAND Flash memory, an embedded MultiMediaCard (eMMC), or any combination thereof.

9. The method of claim 1, further comprising, in response to a transition from the sleep mode to the operating mode:

enabling the portion of the volatile memory device; and

copying the data from the non-volatile memory device to the volatile memory device.

10. The method of claim 9, wherein a memory mapping associated with the data prior to copying the data to the non-volatile memory device remains valid after the data is copied from the non-volatile memory device to the volatile memory device.

11. The method of claim 9, wherein a data element copied from a particular location of the volatile memory device is copied from the non-volatile memory device to the particular location of the volatile memory device after enabling the volatile memory device.

12. The method of claim 9, wherein the electronic device comprises a mobile phone, wherein the volatile memory device is associated with multimedia data, wherein the mobile phone comprises a second volatile memory device associated with modem data, and wherein the second volatile memory device remains enabled during the sleep mode.

13. An apparatus comprising:

a volatile memory device having a first size;

a non-volatile memory device having a second size that is greater than or equal to the first size;

a processor configured to initiate a transition from an operating mode to a sleep mode and to disable a portion of the volatile memory device during the sleep mode; and

a data transfer module configured to copy data from the volatile memory device to the non-volatile memory device in response to the initiating and prior to the disabling of the volatile memory device during the sleep mode.

14. The apparatus of claim 13, wherein the data transfer module comprises hardware that is coupled to the volatile memory device and to the non-volatile memory device and that is configured to copy the data from the volatile memory device to the non-volatile memory device without sending the data to the processor and to copy the data from the non-volatile memory device to the volatile memory device without sending the data to the processor.

15. The apparatus of claim 13, wherein the data transfer module is integrated into the processor, executable by the processor, or any combination thereof.

16. The apparatus of claim 15, wherein the data transfer module is configured to copy the data from the volatile memory device to the non-volatile memory device via the processor and to copy the data from the non-volatile memory device to the volatile memory device via the processor.

17. A computer-readable storage device comprising instructions that, when executed by a processor, cause the processor to:

initiate a transition from an operating mode to a sleep mode at an electronic device, wherein the electronic device comprises a volatile memory device having a first size and a non-volatile memory device having a second size that is greater than or equal to the first size;

in response to the initiating, cause copying of data from the volatile memory device to the non-volatile memory device; and

disable a portion of the volatile memory device during the sleep mode.

18. An apparatus comprising:

a volatile memory device having a first size;

a non-volatile memory device having a second size;

a processor configured to initiate a transition from an operating mode to a sleep mode and to disable a portion of the volatile memory device during the sleep mode; and

means for copying data from the volatile memory device to the non-volatile memory device in response to the initiating and prior to the disabling of the volatile memory device during the sleep mode.

19. A method comprising:

determining that a low performance mode (LPM) condition is satisfied at an electronic device, wherein the electronic device includes a volatile memory device that stores a first copy of read-only data and a non-volatile memory device that stores a second copy of the read-only data; and

in response to the LPM condition being satisfied;

updating a memory mapping of the read-only data from the volatile memory device to the non-volatile memory device;

disabling a portion of the volatile memory device that stores the first copy of the read-only data; and

directing an access request for the read-only data to the non-volatile memory device instead of to the volatile memory device.

20. The method of claim 19, wherein determining that the LPM condition is satisfied comprises determining that a remaining battery life of a battery of the electronic device is less than a threshold.

21. The method of claim 19, wherein determining that the LPM condition is satisfied comprises receiving input requesting a transition to the LPM.

22. The method of claim 19, wherein the first copy of the read-only data is stored at a first physical address of the volatile memory device, wherein the second copy of the read-only data is stored at a second physical address of the non-volatile memory device, and further comprising accessing the read-only data using the second physical address during the LPM.

23. The method of claim 19, further comprising, in response to determining that the LPM condition is no longer satisfied:

enabling the portion of the volatile memory device; and

updating the memory mapping of the read-only data from the non-volatile memory device to the volatile memory device.

24. The method of claim 23, further comprising copying the read-only data from the non-volatile memory device to the volatile memory device prior to updating the memory mapping.

25. The method of claim 19, wherein the non-volatile memory device comprises a NOR Flash memory that supports execute-in-place (XIP) operation, and further comprising, during the LPM, executing one or more instructions of the read-only data from the NOR Flash memory.

26. The method of claim 19, further comprising disabling interrupts before updating the memory mapping and enabling interrupts after updating the memory mapping.

27. The method of claim 19, further comprising suspending thread scheduling at a processor of the electronic device before updating the memory mapping and resuming the thread scheduling after updating the memory mapping.

28. The method of claim 19, further comprising switching from a multi-threaded mode to a single-threaded mode at a processor of the electronic device before updating the memory mapping and switching from the single-threaded mode to the multi-threaded mode after updating the memory mapping.

29. The method of claim 19, further comprising invalidating one or more entries of a translation lookaside buffer (TLB) at a processor of the electronic device before updating the memory mapping.

30. The method of claim 19, wherein disabling the portion of the volatile memory device that stores the first copy of the read-only data comprises disabling refreshing of the portion during the LPM.

31. The method of claim 19, wherein disabling the portion of the volatile memory device that stores the first copy of the read-only data comprises turning off the portion during the LPM.

32. An apparatus comprising:

a volatile memory device storing a first copy of read-only data;

a non-volatile memory device storing a second copy of the read-only data; and

a processor configured to, in a low performance mode (LPM);

update a memory mapping of the read-only data from the volatile memory device to the non-volatile memory device;

disable a portion of the volatile memory device that stores the first copy of the read-only data; and

direct an access request for the read-only data to the non-volatile memory device instead of to the volatile memory device.

33. The apparatus of claim 32, wherein the processor is further configured to determine whether a LPM condition is satisfied.

34. The apparatus of claim 32, wherein the volatile memory device further stores a copy of second read-only data, and wherein the second read-only data is accessed at the volatile memory device during the LPM.

35. The apparatus of claim 32, wherein the volatile memory device further stores a copy of read-write data, and wherein the read-write data is accessed at the volatile memory device during the LPM.

36. The apparatus of claim 35, wherein the read-only data and the read-write data are associated with a particular subsystem of an electronic device, and wherein the read-only data and the read-write data are grouped separately by a linker that generates an image corresponding to the subsystem.

37. A computer-readable storage device comprising instructions that, when executed by a processor, cause the processor to:

in response to a low performance mode (LPM) condition being satisfied at an electronic device, the electronic device including a volatile memory device that stores a first copy of read-only data and a non-volatile memory device that stores a second copy of the read-only data;

update a memory mapping of the read-only data from the volatile memory device to the non-volatile memory device;

disable a portion of the volatile memory device that stores the first copy of the read-only data; and

direct an access request for the read-only data to the non-volatile memory device instead of to the volatile memory device.

38. The computer-readable storage device of claim 37, further comprising instructions that, when executed by the processor, cause the processor to determine that the LPM condition is satisfied.

39. An apparatus comprising:

a volatile memory device storing a first copy of read-only data;

a non-volatile memory device storing a second copy of the read-only data;

means for updating, in response to a low performance mode (LPM) condition being satisfied, a memory mapping of the read-only data from the volatile memory device to the non-volatile memory device;

means for disabling a portion of the volatile memory device that stores the first copy of the read-only data; and

means for directing an access request for the read-only data to the non-volatile memory device instead of to the volatile memory device.

40. The apparatus of claim 39, further comprising means for determining that the LPM condition is satisfied.