THIN FILM TRANSISTOR ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND ELECTRONIC DEVICE

• US 20140183519A1
• Filed: 11/28/2012
• Published: 07/03/2014
• Est. Priority Date: 03/05/2012
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Ning, Ce, Zhang, Xuehui, Yang, Jing
• Granted Patent: US 8,952,387 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

According to embodiments of the present invention, there are provided a TFT array substrate, a method for manufacturing the TFT array substrate and an electronic device. The method for manufacturing the TFT array substrate comprises: a first patterning process, in which a pattern of a pixel electrode formed by a first transparent conductive layer and patterns of a drain electrode and a source electrode that are separated from each other and a data line, which are formed by a first metal layer, are formed on a transparent substrate; a second patterning process, in which a pattern of a gate insulating layer and a pattern of an active layer formed by a transparent oxide layer are formed on the transparent substrate subjected to the first patterning process; and a third patterning process, in which a pattern of a common electrode formed by a second transparent conductive layer and patterns of a gate electrode and a gate line which are formed by a second metal layer are formed on the transparent substrate subjected to the second patterning process.

Claims

1. A method for manufacturing a thin film transistor array substrate, comprising:

a first patterning process, in which a pattern of a pixel electrode formed by a first transparent conductive layer and patterns of a drain electrode and a source electrode that are separated from each other and a data line, which are formed by a first metal layer, are formed on a transparent substrate;

a second patterning process, in which a pattern of a gate insulating layer and a pattern of an active layer formed by a transparent oxide layer are formed on the transparent substrate subjected to the first patterning process; and

a third patterning process, in which a pattern of a common electrode formed by a second transparent conductive layer and patterns of a gate electrode and a gate line which are formed by a second metal layer are formed on the transparent substrate subjected to the second patterning process.

2. The method for manufacturing the thin film transistor array substrate claimed as claim 1, wherein, the first patterning process comprises:

sequentially depositing the first transparent conductive layer and the first metal layer on the transparent substrate;

coating a photoresist layer on the first metal layer; and

etching after exposure and development are performed on the photoresist layer with a double-tone mask, so as to form the patterns of the drain electrode and the source electrode, that are separated from each other, and the data line, which are formed by the first metal layer; and

etching again after an ashing process is performed on the photoresist layer, so as to form the pattern of the pixel electrode formed by the first transparent conductive layer.

3. The method for manufacturing the thin film transistor array substrate claimed as claim 2, wherein the sequentially depositing of the first transparent conductive layer and the first metal layer on the transparent substrate comprises:

depositing the first transparent conductive layer with a thickness in the range of 40˜

70 nm and the first metal layer with a thickness in the range of 200˜

400 nm on the transparent substrate by means of magnetron sputtering.

4. The method for manufacturing the thin film transistor array substrate claimed as claim 3, wherein

IZO or ITO is applicable for the first transparent conductive layer;

and

at least one of Cr, W, Ti, Ta, Mo, Al and Cu is applicable for the first metal layer.

5. The method for manufacturing the thin film transistor array substrate claimed as claim 1, wherein the second patterning process comprises:

sequentially depositing the transparent oxide layer and the gate insulating layer on the transparent substrate subjected to the first patterning process;

coating a photoresist layer on the gate insulating layer; and

etching after exposure and development are performed on the photoresist layer with a double-tone mask, so as to form the pattern of the gate insulating layer; and

etching again after an ashing process is performed on the photoresist layer, so as to form the pattern of the active layer.

6. The method for manufacturing the thin film transistor array substrate claimed as claim 5, wherein the sequentially depositing of the transparent oxide layer and the gate insulating layer on the transparent substrate subjected to the first patterning process comprises:

depositing the transparent oxide layer with a thickness in the range of 20˜

50 nm on the transparent substrate subjected to the first patterning process by means of magnetron sputtering; and

depositing the gate insulating layer with a thickness in the range of 300˜

400 nm on the transparent oxide layer by means of plasma enhanced chemical vapor deposition or magnetron sputtering.

7. The method for manufacturing the thin film transistor array substrate claimed as claim 6, wherein IGZO, ZnO or IZO is applicable for the transparent oxide layer;

when the gate insulating layer is deposited by means of magnetron sputtering, Al2O3 or MN is applicable for the gate insulating layer; and

when the gate insulating layer is deposited by means of plasma enhanced chemical vapor deposition, SiO2 or SiNx is applicable for the gate insulating layer.

8. The method for manufacturing the thin film transistor array substrate claimed as claim 1, wherein the third patterning process comprises:

sequentially depositing the second transparent conductive layer and the second metal layer on the transparent substrate subjected to the second patterning process;

coating a photoresist layer on the second metal layer; and

etching after exposure and development are performed on the photoresist layer with a double-tone mask, so as to form the patterns of the gate electrode and the gate line, which are formed by the second metal layer; and

etching again after an ashing process is performed on the photoresist layer, so as to form the pattern of the common electrode formed by the second transparent conductive layer.

9. The method for manufacturing the thin film transistor array substrate claimed as claim 8, wherein the sequentially depositing of the second transparent conductive layer and the second metal layer on the transparent substrate subjected to the second patterning process comprises:

depositing the second transparent conductive layer with a thickness in the range of 40˜

70 nm and the second metal layer with a thickness in the range of 200˜

400 nm on the transparent substrate subjected to the second patterning process by means of magnetron sputtering.

10. The method for manufacturing the thin film transistor array substrate claimed as claim 9, wherein

IZO or ITO is applicable for the second transparent conductive layer;

at least one of Cr, W, Ti, Ta, Mo, Al and Cu is applicable for the second metal layer.

11. A thin film transistor array substrate, comprising:

a transparent substrate;

a pixel electrode, which is provided on the transparent substrate and formed by a first transparent conductive layer;

a source electrode, a drain electrode and a data line, which are provided on the pixel electrode and formed by a first metal layer;

an active layer, which is provided on the transparent substrate and formed by a transparent oxide layer;

a gate insulating layer, which is provided on the active layer;

a common electrode, which is provided on the gate insulating layer and formed by a second transparent conductive layer; and

a gate electrode and a gate line, which are provided on the common electrode and formed by a second metal layer.

12. An electronic device comprising the thin film transistor array substrate claimed as claim 11.