PARASITIC INDUCTANCE REDUCTION FOR MULTILAYERED BOARD LAYOUT DESIGNS WITH SEMICONDUCTOR DEVICES

• US 20140183550A1
• Filed: 12/27/2013
• Published: 07/03/2014
• Est. Priority Date: 12/31/2012
• Status: Active Grant

• Current Assignee: Efficient Power Conversion Corporation
• Original Assignee: Efficient Power Conversion Corporation
• Inventors: Strydom, Johan Tjeerd, Reusch, David
• Granted Patent: US 9,035,417 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H02M 7/003 Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/0243 Printed circuits associated with mounted high frequency components
• CPC Class Codes: H05K 1/0265 characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections
• CPC Class Codes: H05K 2201/0792 Means against parasitic impedance; Means against eddy currents
• CPC Class Codes: H05K 2201/10166 Transistor

Abstract

A highly efficient, single sided circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop extends through active and passive devices on the top layer of the circuit board, with vias connecting the power loop to a return path in an inner layer of the board. The magnetic effect of the portion of the power loop on the top layer is reduced by locating the inner layer return path directly underneath the power loop path on the top layer.

Claims

1. A circuit board for circuits including at least one passive device and at least one active device, comprising:

a top layer on which the passive device and the active device are mounted and electrically connected as part of a power loop,

a bottom layer; and

an inner layer having an electrical path connected to the top layer through vias, such that the inner layer serves as a return path of the power loop on the top layer.

2. The circuit board of claim 1, wherein the return path of the inner layer is located so as to reduce the magnetic effect of the power loop of the top layer.

3. The circuit board of claim 1, wherein the inner layer return path is located directly underneath the path of the power loop of the top layer.

4. The circuit board of claim 1, wherein both the active and passive devices, and capacitance, are located on the top layer of the circuit board.

5. The circuit board of claim 1, wherein the active device is a GaN transistor.

6. The circuit board of claim 1, wherein the passive device forms a switching circuit with the active device.

7. The circuit board of claim 1, wherein the passive device and the active device are components of a switching circuit.

8. The circuit board of claim 1, wherein the passive device and the active device are components of a power converter.

9. The circuit board of claim 1, wherein the passive device and the active device are components of a RF amplifier.