TRANSISTOR STRUCTURES HAVING A DEEP RECESSED P+ JUNCTION AND METHODS FOR MAKING SAME

• US 20140183552A1
• Filed: 12/28/2012
• Published: 07/03/2014
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Zhang, Qingchun, Hull, Brett
• Granted Patent: US 10,115,815 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SIC) MOSFET device.

Claims

1. A transistor device comprising a gate and a source on an upper surface of the transistor device, wherein the transistor device further comprises at least one doped well region;

the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device; and

the at least one doped well region is recessed from the upper surface of the transistor device by a depth sufficient to reduce an electrical field on a gate oxide on the gate.

2. A transistor device according to claim 1, wherein a body of the transistor device comprises silicon carbide.

3. A transistor device according to claim 1, wherein the at least one doped well region is a P+ implanted junction.

4. A transistor device according to claim 1, wherein the at least one doped well region is in a source contact area of the transistor device.

5. A transistor device according to claim 1, wherein the transistor device has no termination area.

6. A transistor device according to claim 1, wherein the transistor device further comprises a termination area that includes at least one termination structure and the at least one doped well region is a P+ implanted junction that is recessed deeper than the termination structure.

7. A transistor device according to claim 1, wherein the depth is sufficient to result in an avalanche path to occur wholly within an active area of the transistor device instead of a termination device.

8. A transistor device according to claim 1, wherein the depth is about approximately 0/microns to about approximately 1.5 microns.

9. A transistor device according to claim 1, wherein the depth is about approximately 0.7 microns to about approximately 0.9 microns.

10. A transistor device according to claim 1, wherein the depth is about approximately 0.9 microns to about approximately 1.1 microns.

11. A transistor device according to claim 1, wherein the depth is about approximately 1.1 microns to about approximately 1.3 microns.

12. A transistor device according to claim 1, wherein the transistor device is an MOSFET.

13. A transistor device according to claim 1, wherein the transistor device is an insulated gate bipolar transistor.

14. A transistor device according to claim 1, wherein the transistor device is a metal-oxide-semiconductor controlled thyristor

15. A transistor device according to claim 1, wherein the first conductivity type is P+, and the second conductivity type is N+.

16. A transistor device comprising at least one sidewall and an upper surface, wherein a gate and a source are at least partially disposed on the upper surface, the transistor device comprising:

at least one source region of a first conductivity type; and

at least one well region of a second conductivity type adjacent to the at least one source region, the at least one well region being recessed from the upper surface of the transistor device to a depth,

wherein at least a portion of the upper surface and the sidewall of the transistor device is etched away to a recess depth as measured from the upper surface.

17. A transistor device according to claim 16, wherein a body of the transistor device comprises silicon carbide.

18. A transistor device according to claim 16, wherein the at least one well region is a P+ implanted junction.

19. A transistor device according to claim 16, wherein at least a portion of the at least one source region is etched away.

20. A transistor device according to claim 16, wherein at least a portion of the at least one well region is etched away.

21. A transistor device according to claim 16, wherein the transistor device has no termination area.

22. A transistor device according to claim 16, wherein the recess depth is sufficient to result in an avalanche path to occur wholly within an active area of the transistor device instead of a termination device.

23. A transistor device according to claim 16, wherein the transistor device further comprises a gate oxide on the gate and wherein the recess depth is sufficient to reduce an electrical field on the gate oxide.

24. A transistor device according to claim 16, wherein the recess depth is about approximately 0.2 microns to about approximately 1.0 microns.

25. A transistor device according to claim 16, wherein the recess depth is about approximately 0.2 microns to about approximately 0.4 microns.

26. A transistor device according to claim 16, wherein the recess depth is about approximately 0.4 microns to about approximately 0.6 microns.

27. A transistor device according to claim 16, wherein the depth is about approximately 0.6 microns to about approximately 0.8 Microns.

28. A transistor device according to claim 16, wherein the transistor device is an MOSFET.

29. A transistor device according to claim 16, wherein the transistor device is an insulated gate bipolar transistor.

30. A transistor device according to claim 16, wherein the transistor device is a metal-oxide-semiconductor controlled thyristor

31. A transistor device according to claim 16, wherein the at least one source region is a N+ source region, and the at least one well region is a P+ well region.

32. A transistor device according to claim 16, wherein a large ohmic contact area is formed in an area of the source region when at least a portion of the upper surface and the sidewall of the transistor device is etched away to a recess depth.

33. A method of forming a transistor device having at least one sidewall and an upper surface, comprising:

providing a gate and a source on the upper surface;

providing at least one source region of a first conductivity type;

providing at least one well region of a second conductivity type adjacent to the at least one source region, the at least one well region being recessed from the upper surface of the transistor device to a depth; and

etching at least a portion of the upper surface and the sidewall of the transistor device to a recess depth as measured from the upper surface.

34. A method according to claim 33, wherein a body of the transistor device comprises silicon carbide.

35. A method according to claim 33, wherein providing the at least one well region comprises implanting a P+ implanted junction.

36. A method according to claim 33, further comprising etching away at least a portion of the at least one source region.

37. A method according to claim 33, further comprising etching away at least a portion of the at least one well region.

38. A method according to claim 33, wherein the method does not include forming a termination area.

39. A method according to claim 33, wherein the depth is sufficient to result in an avalanche path to occur wholly within an active area of the transistor device instead of a termination device.

40. A method according to claim 33, wherein the transistor device further comprises a gate oxide on the gate and wherein the depth is sufficient to reduce an electrical field on the gate oxide.

41. A method according to claim 33, wherein the depth is about approximately 0.2 microns to about approximately 1.0 microns.

42. A method according to claim 33, wherein the depth is about approximately 0.2 microns to about approximately 0.4 microns.

43. A method according to claim 33, wherein the depth is about approximately 0.4 microns to about approximately 0.6 microns.

44. A method according to claim 33, wherein the depth is about approximately 0.6 microns to about approximately 0.8 microns.