NOVEL FIN STRUCTURE OF FINFET

• US 20140183600A1
• Filed: 12/28/2012
• Published: 07/03/2014
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Gin-Chen, Jiang, Ching-Hong, Chen, Neng-Kuo, Sun, Sey-Ping, Wann, Clement Hsingjen
• Granted Patent: US 9,093,530 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature.

Claims

1. A fin structure, comprising:

a mesa having a first semiconductor material;

a channel disposed over the mesa, wherein the channel has a second semiconductor material different from the first semiconductor material; and

a convex-shaped feature disposed between the channel and the mesa.

2. The fin structure of claim 1, wherein the convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped.

3. The fin structure of claim 1, wherein the convex-shaped feature comprises:

a first isolation feature disposed between the channel and the mesa; and

a second isolation feature disposed between the channel and the first isolation feature.

4. The fin structure of claim 3, wherein the first isolation feature is U-shaped.

5. The fin structure of claim 3, wherein the second isolation feature is rectangular-shaped.

6. The fin structure of claim 3, wherein a portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature.

7. The fin structure of claim 3, wherein a thickness of the first isolation feature ranges from about 1 nm to about 10 nm.

8. The fin structure of claim 3, wherein a ratio of a height of the first isolation feature to a width of the first isolation feature ranges from about 2 to about 99.

9. The fin structure of claim 3, wherein a ratio of a height of the second isolation feature to a width of the second isolation feature ranges from about 1 to about 166.

10. The fin structure of claim 3, wherein the first isolation feature has a first dielectric material and the second isolation feature has a second dielectric material different from the first dielectric material.

11. The fin structure of claim 10, wherein the first dielectric material comprises nitride.

12. The fin structure of claim 10, wherein the second dielectric material comprises oxide.

13. A fin field-effect transistor (FinFET), comprising:

a mesa having a first semiconductor material;

a channel disposed over the mesa, wherein the channel has a second semiconductor material different from the first semiconductor material;

a U-shaped feature disposed between the channel and the mesa;

a rectangular-shaped feature disposed between the channel and the U-shaped feature;

a gate dielectric disposed over the channel; and

a gate electrode disposed over the gate dielectric.

14. The FinFET of claim 13, wherein a portion of the rectangular-shaped feature is surrounded by the channel and another portion of the rectangular-shaped feature is surrounded by the U-shaped feature.

15. The FinFET of claim 13, wherein a thickness of the U-shaped feature ranges from about 1 nm to about 10 nm.

16. The FinFET of claim 13, wherein a ratio of a height of the U-shaped feature to a width of the U-shaped feature ranges from about 2 to about 99.

17. The FinFET of claim 13, wherein a ratio of a height of the rectangular-shaped feature to a width of the rectangular-shaped feature ranges from about 1 to about 166.

18. The FinFET of claim 13, wherein the U-shaped feature has a first dielectric material and the rectangular-shaped feature has a second dielectric material different from the first dielectric material.

19. A method of forming a fin structure, comprising:

forming a mesa having a first semiconductor material;

forming a first isolation feature over the mesa;

forming a second isolation feature over the first isolation feature; and

forming a channel over the first isolation feature, the second isolation feature, and the mesa, wherein the channel has a second semiconductor material different from the first semiconductor material.

20. The method of claim 19, wherein the forming the first isolation feature and the forming the second isolation feature comprise:

forming a concave portion in the mesa, wherein the concave portion has a bottom surface and a sidewall;

forming a first dielectric layer over the bottom surface, the sidewall, the mesa, and a top surface of a shallow trench isolation (STI) structure, wherein the first dielectric layer has an upper part over the top surface and a lower part below the top surface;

forming a second dielectric layer over the first dielectric layer, wherein the second dielectric layer has an upper segment over the top surface and a lower segment below the top surface;

removing the upper segment and a portion of the lower segment to form the second isolation feature; and

removing the upper part and a portion of the lower part to form the first isolation feature;

wherein a height of the second isolation feature is greater than a height of the first isolation feature.