Adaptive Charge Balanced MOSFET Techniques
First Claim
Patent Images
1. An apparatus comprising:
- a drain region;
a drift region disposed on the drain region;
a plurality of body regions disposed on the drift region opposite the drain region;
a plurality of source regions disposed on the plurality of body regions opposite the drift region, wherein the plurality of source regions, the plurality of body regions and the drift regions are adjacent a plurality of gate structures;
the plurality of gate structures, wherein each gate structure includes;
a plurality of substantially parallel elongated gate regions extending through the plurality of source regions and the plurality of body regions and extending partially into the drift region; and
a plurality of gate insulator regions each disposed between a respective one of the plurality of gate regions and the plurality of source regions, the plurality of body regions and the drift regiona plurality of field plate structures, wherein each field plate structure is disposed through the body regions and extending into the drift region, wherein each gate structure is disposed between a set of field plate structures, and wherein each field plate structure includes;
a plurality of field plate insulator regions;
a plurality of field plate regions, wherein the plurality of field plate regions are interspersed between the plurality of held plate insulator regions; and
a field ring region disposed between the plurality of field plate regions and the adjacent drift regions, and wherein a set of field plates are coupled to the field ring region.
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Abstract
An adaptive charge balanced MOSFET device includes a field plate stacks, a gate structure, a source region, a drift region and a body region. The gate structure includes a gate region surrounded by a gate insulator region. The field plate stack includes a plurality of field plate insulator regions, a plurality of field plate regions, and a field ring region. The plurality of field plates are separated from each other by respective field plate insulators. The body region is disposed between the gate structure, the source region, the drift region and the field ring region. Each of two or more field plates are coupled to the field ring.
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Citations
20 Claims
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1. An apparatus comprising:
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a drain region; a drift region disposed on the drain region; a plurality of body regions disposed on the drift region opposite the drain region; a plurality of source regions disposed on the plurality of body regions opposite the drift region, wherein the plurality of source regions, the plurality of body regions and the drift regions are adjacent a plurality of gate structures; the plurality of gate structures, wherein each gate structure includes; a plurality of substantially parallel elongated gate regions extending through the plurality of source regions and the plurality of body regions and extending partially into the drift region; and a plurality of gate insulator regions each disposed between a respective one of the plurality of gate regions and the plurality of source regions, the plurality of body regions and the drift region a plurality of field plate structures, wherein each field plate structure is disposed through the body regions and extending into the drift region, wherein each gate structure is disposed between a set of field plate structures, and wherein each field plate structure includes; a plurality of field plate insulator regions; a plurality of field plate regions, wherein the plurality of field plate regions are interspersed between the plurality of held plate insulator regions; and a field ring region disposed between the plurality of field plate regions and the adjacent drift regions, and wherein a set of field plates are coupled to the field ring region. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A metal-oxide-semiconductor field effect transistor comprising:
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a field plate stack including; a plurality of field plate insulator regions; a plurality of field plate regions, wherein the plurality of field plates are interspersed between the plurality of field plate insulators; and a field ring region, wherein each of two or more field plates are coupled to the field ring; a gate structure including a gate region surrounded by a gate insulator region; a source region; a drill region; a body region disposed between the gate structure, the source region, the drift region and the field ring region. - View Dependent Claims (8, 9, 11, 12, 13)
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14. A method comprising:
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forming a semiconductor layer moderately doped with a first type of dopant on a semiconductor layer heavily doped with the first type of dopant; forming a plurality of field plate stack trenches in the semiconductor layer lightly doped with the first type of dopant; forming a semiconductor region heavily doped with a second type of dopant in the semiconductor layer moderately doped with the first type of dopant along the walls of the field plate stack trenches; forming a first dielectric layer in the field plate stack trenches; forming a first semiconductor layer heavily doped with the second type of dopant on the first dielectric layer in the field plate stack trenches, wherein a portion of the first semiconductor layer contacts a first portion of the semiconductor region heavily doped with the second type of dopant; forming a second dielectric layer on the first semiconductor layer heavily doped with the second type of dopant in the field plate stack trenches; forming a second semiconductor layer heavily doped with the second type of dopant on the second dielectric layer in the field plate stack trenches, wherein a portion of the second semiconductor layer contacts a second portion of the semiconductor region heavily doped with the second type of dopant; forming a plurality of gate trenches in the semiconductor layer lightly doped with the first type of dopant; forming a dielectric layer in the gate trenches; forming a semiconductor layer heavily doped with the first type of dopant on the dielectric layer in the gate trenches; forming a semiconductor region moderately doped with the second type of dopant in the semiconductor layer moderately doped with the first type of dopant opposite the semiconductor layer heavily doped with the first type of dopant and between the dielectric layer in the gate trenches and the semiconductor region heavily doped with the second type of dopant along the walls of the field plate stack trenches; and forming a semiconductor region heavily doped with the first type of dopant in the semiconductor region moderately doped with the second type of dopant opposite the semiconductor layer lightly doped with the first type of dopant adjacent the dielectric layer in the gate trenches, but separated from the semiconductor region heavily doped with the second type of dopant along the wall of the field plate stack trenches by the semiconductor region moderately doped with the second type of dopant. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification