Adaptive Charge Balanced MOSFET Techniques

• US 20140183624A1
• Filed: 12/31/2012
• Published: 07/03/2014
• Est. Priority Date: 12/31/2012
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Tipirneni, Naveen, Pattanayak, Deva N.
• Granted Patent: US 9,853,140 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

An adaptive charge balanced MOSFET device includes a field plate stacks, a gate structure, a source region, a drift region and a body region. The gate structure includes a gate region surrounded by a gate insulator region. The field plate stack includes a plurality of field plate insulator regions, a plurality of field plate regions, and a field ring region. The plurality of field plates are separated from each other by respective field plate insulators. The body region is disposed between the gate structure, the source region, the drift region and the field ring region. Each of two or more field plates are coupled to the field ring.

Claims

1. An apparatus comprising:

a drain region;

a drift region disposed on the drain region;

a plurality of body regions disposed on the drift region opposite the drain region;

a plurality of source regions disposed on the plurality of body regions opposite the drift region, wherein the plurality of source regions, the plurality of body regions and the drift regions are adjacent a plurality of gate structures;

the plurality of gate structures, wherein each gate structure includes;

a plurality of substantially parallel elongated gate regions extending through the plurality of source regions and the plurality of body regions and extending partially into the drift region; and

a plurality of gate insulator regions each disposed between a respective one of the plurality of gate regions and the plurality of source regions, the plurality of body regions and the drift region

a plurality of field plate structures, wherein each field plate structure is disposed through the body regions and extending into the drift region, wherein each gate structure is disposed between a set of field plate structures, and wherein each field plate structure includes;

a plurality of field plate insulator regions;

a plurality of field plate regions, wherein the plurality of field plate regions are interspersed between the plurality of held plate insulator regions; and

a field ring region disposed between the plurality of field plate regions and the adjacent drift regions, and wherein a set of field plates are coupled to the field ring region.

2. The apparatus according to claim 1, wherein:

the drain region comprises a heavily n-doped semiconductor;

the drift region comprises a moderate n-doped semiconductor;

the plurality of body regions comprise a moderately p-doped semiconductor;

the plurality of source regions comprise as heavily n-doped semiconductor;

the plurality of field plate regions comprise a heavily p-doped semiconductor; and

the plurality of field ring regions comprise a heavily p-doped semiconductor.

3. The apparatus according to claim 1, wherein:

the drain region comprises a heavily p-doped semiconductor;

the drift region comprises a moderately p-doped semiconductor;

the plurality of body regions comprise a moderately n-doped semiconductor;

the plurality of source regions comprise a heavily p-doped semiconductor;

the plurality of field plate regions comprise a heavily n-doped semiconductor;

the plurality of field ring regions comprise a heavily n-doped semiconductor.

4. The apparatus according to claim 1, wherein each of the plurality of field ring regions each comprise multiple portions wherein two or more portions of the field ring region are coupled to a corresponding field plate region.

5. The apparatus according to claim 1, further comprising a source/body/field plate contact disposed on the source region, the body region and one of the plurality of field plate regions.

6. The apparatus according to claim 2, wherein the plurality of field plate regions are in Schottky contact with the drift regions increasing a breakdown voltage of the apparatus as compared to an ohmic contact.

7. A metal-oxide-semiconductor field effect transistor comprising:

a field plate stack including;

a plurality of field plate insulator regions;

a plurality of field plate regions, wherein the plurality of field plates are interspersed between the plurality of field plate insulators; and

a field ring region, wherein each of two or more field plates are coupled to the field ring;

a gate structure including a gate region surrounded by a gate insulator region;

a source region;

a drill region;

a body region disposed between the gate structure, the source region, the drift region and the field ring region.

8. The metal-oxide-semiconductor field effect transistor according to claim 7, wherein the field ring region comprises multiple portions wherein two or more portions of the field ring region each couple a corresponding field plate region to an adjacent portion of the body region.

9. The metal-oxide-semiconductor field effect transistor according to claim 7, wherein:

the drift region comprises epitaxial silicon moderately doped with phosphorous or arsenic;

the plurality of body regions comprise silicon moderately doped with boron;

the plurality of source regions comprise silicon heavily doped with phosphorous or arsenic;

the plurality of gate regions comprise polysilicon heavily doped with phosphorous or arsenic;

the plurality of field plate regions comprise polysilicon heavily doped with boron; and

the plurality of field ring regions comprise epitaxial silicon heavily doped with boron.

11. The metal-oxide-semiconductor field effect transistor according to claim 7, wherein:

the drift region comprises epitaxial silicon moderately doped with boron;

the plurality of body regions comprise silicon moderately doped with phosphorous or arsenic;

the plurality of source regions comprise silicon heavily doped with boron;

the plurality of gate regions comprise polysilicon heavily doped with boron;

the plurality of field plate regions comprise polysilicon heavily doped with phosphorous or arsenic; and

the plurality of field ring regions comprise epitaxial silicon heavily doped with phosphorous or arsenic.

12. The metal-oxide-semiconductor field effect transistor according to claim 7, wherein a depth of the field plate stack is greater than a depth of the gate structure.

13. The metal-oxide-semiconductor field effect transistor according to claim 7, wherein a thickness of the field plate insulator region and the contact area between the field plate regions and the field ring region are selected so that each field plate region floats to a different potential when a drain voltage is greater than as pinch-off voltage.

14. A method comprising:

forming a semiconductor layer moderately doped with a first type of dopant on a semiconductor layer heavily doped with the first type of dopant;

forming a plurality of field plate stack trenches in the semiconductor layer lightly doped with the first type of dopant;

forming a semiconductor region heavily doped with a second type of dopant in the semiconductor layer moderately doped with the first type of dopant along the walls of the field plate stack trenches;

forming a first dielectric layer in the field plate stack trenches;

forming a first semiconductor layer heavily doped with the second type of dopant on the first dielectric layer in the field plate stack trenches, wherein a portion of the first semiconductor layer contacts a first portion of the semiconductor region heavily doped with the second type of dopant;

forming a second dielectric layer on the first semiconductor layer heavily doped with the second type of dopant in the field plate stack trenches;

forming a second semiconductor layer heavily doped with the second type of dopant on the second dielectric layer in the field plate stack trenches, wherein a portion of the second semiconductor layer contacts a second portion of the semiconductor region heavily doped with the second type of dopant;

forming a plurality of gate trenches in the semiconductor layer lightly doped with the first type of dopant;

forming a dielectric layer in the gate trenches;

forming a semiconductor layer heavily doped with the first type of dopant on the dielectric layer in the gate trenches;

forming a semiconductor region moderately doped with the second type of dopant in the semiconductor layer moderately doped with the first type of dopant opposite the semiconductor layer heavily doped with the first type of dopant and between the dielectric layer in the gate trenches and the semiconductor region heavily doped with the second type of dopant along the walls of the field plate stack trenches; and

forming a semiconductor region heavily doped with the first type of dopant in the semiconductor region moderately doped with the second type of dopant opposite the semiconductor layer lightly doped with the first type of dopant adjacent the dielectric layer in the gate trenches, but separated from the semiconductor region heavily doped with the second type of dopant along the wall of the field plate stack trenches by the semiconductor region moderately doped with the second type of dopant.

15. The method of claim 14, further comprising:

forming a third dielectric layer on the second semiconductor layer heavily doped with the second type of dopant in the field plate stack trenches; and

forming a third semiconductor layer heavily doped with the second type of dopant on the third dielectric layer in the field plate stack trenches, wherein a portion of the third semiconductor layer contacts a third portion of the semiconductor region heavily doped with the second type of dopant.

16. The method of claim 15, further comprising:

forming a fourth dielectric layer on the third semiconductor layer heavily doped with the second type of dopant in the field plate stack trenches; and

forming a fourth semiconductor layer heavily doped with the second type of dopant on the fourth dielectric layer in the field plate stack trenches.

17. The method of claim 14, wherein forming the first dielectric layer and the first semiconductor layer in the field plate stack trenches comprises:

growing a first dielectric layer in the field plate stack trenches;

depositing a portion of the first semiconductor layer heavily doped with the second type of dopant in the field plate stack trenches;

etching back the portion of the first semiconductor layer heavily doped with the second type of dopant in the field plate stack trenches to a first predetermined thickness;

etching back the first dielectric layer in the field plate stack trenches to the first predetermined thickness of the portion of the first semiconductor layer heavily doped with the second type of dopant in the field plate stack trenches;

depositing an other portion of the first semiconductor layer heavily doped with the second type of dopant in the field plate stack trenches; and

etching back the other portion of the first semiconductor layer heavily doped with the second type of dopant in the field plate stack trenches to a second predetermined thickness, wherein the other portion of the first semiconductor layer heavily doped with the second type of dopant of the second predetermined thickness contacts the first portion of the semiconductor region heavily doped with the second of dopant.

18. The method of claim 14, wherein forming the semiconductor region heavily doped with the second type of dopant in the semiconductor layer lightly doped with the first type of dopant along the walls of the field plate stack trenches comprises angle implanting the second type of dopant into the semiconductor layer lightly doped with the first type of dopant along the walls of the field plate stack trenches.

19. The method of claim 14, wherein forming the semiconductor region heavily doped with the second type of dopant in the semiconductor layer lightly doped with the first type of dopant along the walls of the field plate stack trenches further comprises:

forming a first semiconductor region heavily doped with the second type of dopant in the semiconductor layer lightly doped with the first type of dopant along the walls of the field plate stack trenches adjacent the portion of the first semiconductor layer heavily doped with the second type of dopant in the field plate stack trenches; and

forming a second semiconductor region heavily doped with the second type of dopant in the semiconductor region moderately doped with the second type of dopant along the wall of the field plate stack trenches adjacent the portion of the second semiconductor layer heavily doped with the second type of dopant in the field plate stack trenches.

20. The method of claim 19, wherein forming the first semiconductor regions heavily doped with the first type of dopant in the semiconductor layer lightly doped with the first type of dopant along the walls of the field plate stack trenches and forming a second semiconductor region heavily doped with the second type of dopant in the semiconductor region moderately doped with the second type of dopant along the wall of the field plate stack trenches comprises out diffusing the second type of dopant from the first semiconductor layer heavily doped with the second type of dopant in the field plate stack trenches and the second semiconductor layer heavily doped with the second type of dopant in the field plate stack trenches.