HIGH EFFICIENCY FINFET DIODE

• US 20140183641A1
• Filed: 07/25/2013
• Published: 07/03/2014
• Est. Priority Date: 12/31/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Sun-Jay, Hu, Chia-Hsin, Liang, Min-Chang, Wu, Shien-Yang, Hsieh, Wen-Hsing, Huang, Ching-Fang, Fan, Hsueh-Shih
• Granted Patent: US 9,093,566 B2
• Time in Patent Office: Days
• US Class Current: 257/365
• CPC Class Codes: H01L 21/0257 Doping during depositing
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/861 Diodes

Abstract

Disclosed are a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.

Claims

1. A semiconductor device comprising:

a substrate having opposing first and second ends;

first and second groups of one or more substantially parallel, elongated, equal numbered semiconductor fin structures disposed upon the substrate adjacent the first and the second ends, respectively, the first and second groups being spaced apart from each other;

one or more substantially equal-spaced and parallel elongated gate structures formed upon the first and the second group fin structures such that each gate structure traverses both the first and the second group fin structures perpendicularly;

a plurality of dielectric strips interwovenly disposed among the first and the second groups of fin structures for electric insulation from one another;

a first group of one or more doped semiconductor strips having a first conductivity type and formed lengthwise upon the first group fin structures, respectively; and

a second group of one or more second doped semiconductor strips having a second conductivity type opposite the first conductivity type and formed lengthwise upon the second group fin structures, respectively, wherein the first group semiconductor strips are electrically insulated from the second group semiconductor strips.

2. The semiconductor device of claim 1, wherein each of the first and the second groups of semiconductor strips is sectioned by the gate structures.

3. The semiconductor device of claim 1, further comprising one or more metal contacts formed upon the first and the second groups of semiconductor strips.

4. The semiconductor device of claim 3, wherein all semiconductor strips in the first group are electrically connected to one another via the metal contacts.

5. The semiconductor device of claim 1, wherein the substrate is implanted with a dopant of either the first conductivity type or the second conductivity type.

6. The semiconductor device of claim 1, wherein the first and the second groups of semiconductor strips are integrally formed with the respective first and second group fin structures by epitaxial growth.

7. The semiconductor device of claim 1, wherein the first and the second groups of semiconductor strips are in-situ doped.

8. The semiconductor device of claim 1, wherein the number of the fin structures in a unit cell is 4, 6, or 8.

9. A FinFET diode comprising:

a semiconductor substrate doped to have either a first conductivity type or a second conductivity type opposite the first conductivity type;

a first group and a second group of substantially equal-spaced, parallel, elongated, and equal numbered semiconductor fin structures formed over the substrate, the first and second groups being spaced-apart and electrically insulated from each other, and the fin structures in each group being electrically insulated from one another; and

a plurality of substantially equal-spaced and parallel elongated gate structures formed upon the first and the second groups of fin structures such that each gate structure traverses both the first and the second groups of fin structures perpendicularly,

wherein a top portion of each of the first group fin structures is doped to have the first conductivity type and a top portion of each of the second group fin structures is doped to have the second conductivity type.

10. The FinFET diode of claim 9, wherein the top portions of the first and the second groups of fin structures are sectioned by the gate structures.

11. The FinFET diode of claim 9, further comprising one or more metal contacts formed upon the doped top portions of the first and the second groups of fin structures.

12. The FinFET diode of claim 9, wherein the spacing between two closest fin structures, each of which is respectively from the first and second groups, is greater than the average spacing between two adjacent fin structures within the respective first and second groups.

13. The FinFET diode of claim 9, wherein the number of the fin structures in a unit cell is 4, 6, or 8.

14. A method of forming a semiconductor device, the method comprising:

providing a substrate having opposing first and second ends;

forming a first and a second groups of one or more substantially equal-spaced, parallel, elongated, and equal numbered semiconductor fin structures upon the substrate adjacent the first and the second ends, respectively, the first and second groups being spaced apart from each other;

forming a plurality of dielectric strips to be interwovenly disposed among the first and the second groups of fin structures for electric insulation from one another;

implanting the substrate with a dopant of either a first conductivity type or a second conductivity type opposite the first conductivity type;

forming one or more substantially equal-spaced and parallel elongated gate structures formed upon the first and the second groups of fin structures such that each gate structure traverses both the first and the second groups of fin structures perpendicularly;

forming a first group of one or more doped semiconductor strips having the first conductivity type lengthwise upon the first group of fin structures, respectively; and

forming a second group of one or more second doped semiconductor strips having the second conductivity type lengthwise upon the second group of fin structures, respectively, wherein the first group of semiconductor strips are electrically insulated from the second group of semiconductor strips.

15. The method of claim 14, wherein each of the first and the second group of semiconductor strips is sectioned by the gate structures.

16. The method of claim 14, further comprising forming one or more metal contacts upon the first and the second group of semiconductor strips, respectively.

17. The method of claim 16, wherein all semiconductor strips in the first and the second groups are electrically connected from one another within the respective groups via the metal contacts.

18. The method of claim 14, wherein forming the first and the second groups of semiconductor strips comprises forming the same integrally with the respective first and second groups of fin structures by epitaxial growth.

19. The method of claim 18, wherein forming the first and the second groups of semiconductor strips further comprises in-situ doping the first and the second groups of semiconductor strips during the epitaxial growth.

20. The method of claim 14, wherein the number of the fin structures in a unit cell is 4, 6, or 8.