SYSTEM, A METHOD AND A COMPUTER PROGRAM PRODUCT FOR ELECTRONIC SUB-INTEGER FREQUENCY DIVISION

• US 20140184281A1
• Filed: 12/27/2012
• Published: 07/03/2014
• Est. Priority Date: 12/27/2012
• Status: Active Grant

• Current Assignee: Ay Dee Kay LLC
• Original Assignee: International Business Machines Corporation
• Inventors: Danny, Elad, Katz, Oded, Levinger, Run
• Granted Patent: US 8,988,119 B2
• Time in Patent Office: Days
• US Class Current: 327/115
• CPC Class Codes: H03K 23/507 with a base which is a non-integer
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/1803 the counter or frequency divider being connected to a cycle or pulse swallowing circuit

Abstract

An electronic sub-integer frequency divider circuit, including: a phase rotator circuit, a clock circuitry, a pulse generator which is configured to: (a) receive a plurality of signals having a period TP and of different phases; (b) based on a control command, to process a second clock signal and one or more of the plurality of signals, to produce a second signal which includes S pulses in each period TP; and (c) process the second signal and a first clock signal to produce a regulating signal by which the phase rotator circuit is controlled; and an output interface configured to provide a sub-integer output signal whose frequency is responsive to the regulating signal.

Claims

1. An electronic sub-integer frequency divider circuit, comprising:

a phase rotator circuit configured to rotatably output, at a rate determined by a rate of pulses in a regulating signal, one or more of a plurality of phase-shift states having a frequency f_A, thereby producing a first signal whose frequency is determined by the frequency f_A and by the regulating signal;

a clock circuitry configured to process the first signal to produce a first clock signal and a second clock signal which is different from the first clock signal;

a pulse generator configured to;

(a) receive a plurality of M signals having a period TP and of different phases;

wherein the period TP is longer than the periods of the first and the second clock signals;

(b) based on a control command, to process the second clock signal and one or more of the M signals, to produce a second signal which includes S pulses in each period TP; and

(c) process the second signal and the first clock signal to produce the regulating signal so that it includes Q pulses in each period TP, wherein Q is different from S; and

an output interface configured to provide a sub-integer output signal whose frequency is responsive to the regulating signal.

2. The electronic sub-integer frequency divider circuit according to claim 1, comprising a phase rotator controller configured to generate, based on the rate of pulses in the regulating signal, control signals for the phase rotator circuit;

wherein the phase rotator circuit is configured to rotatably output the one or more phase-shift states at a rate determined by the control signals, thereby producing a first signal whose frequency is determined by the frequency f_A and by the control signals.

3. The electronic sub-integer frequency divider circuit according to claim 1, wherein the clock circuitry is configured to process the first clock signal to produce the second clock signal.

4. The electronic sub-integer frequency divider circuit according to claim 1, wherein the pulse generator is configured to produce the regulating signal based on the control command, so that the regulating signal includes Q pulses in each period TP if the control command fulfils a first criterion, and S pulses in each period TP otherwise.

5. The electronic sub-integer frequency divider circuit according to claim 1, wherein the pulse generator is configured to produce the regulating signal by processing the second signal and another signal to provide the regulating signal so that Q=S+G, wherein G is a preconfigured fixed number.

6. The electronic sub-integer frequency divider circuit according to claim 5, further comprising:

a prescaler circuit having a dividing factor A, being configured to receive an input signal of the electronic sub-integer frequency divider circuit and to process it to produce the plurality of phase-shifted signals from which the phase-shifted states are generated;

an integer divider having a dividing factor B, being configured to process the first signal to produced the first clock signal;

an integer divider having a dividing factor C, being configured to process the first clock signal to produce the second clock signal; and

an integer divider having a dividing factor P, being configured to process the second clock signal to produce the plurality of M signals;

wherein the electronic sub-integer frequency divider circuit has a sub-integer-dividing factor equal to A·

(BCP+(Δ

φ

/2π

)·

(S+b*G)), where Δ

φ

denotes a minimum phase shift possible from the phase rotator and where b is equal to 0 if the second signal is used as the regulating signal or 1 if the other signal is used in the producing of the regulating signal, and wherein A, B, C and P are integer values ≧

1.

7. The electronic sub-integer frequency divider circuit according to claim 6, wherein the pulse generator is configured to process at least the first clock signal to produce a third signal which includes a preconfigured fixed number Y of pulses;

wherein the pulse generator comprises a multiplexer MX2 that is configured to alternate between the second signal and the third signal to produce the regulating signal.

8. The electronic sub-integer frequency divider circuit according to claim 7, wherein the second clock signal clocks the multiplexer MX2.

9. The electronic sub-integer frequency divider circuit according to claim 1, wherein the second clock signal is produced from the first clock signal by an integer frequency divider.

10. The electronic sub-integer frequency divider circuit according to claim 1, wherein the first clock signal and the second clock signal are non-overlapping signals having the same period.

11. The electronic sub-integer frequency divider circuit according to claim 1, wherein the plurality of M signals are produced from the second clock signal by an integer divider that is coupled to the clock circuitry and to the pulse generator.

12. The electronic sub-integer frequency divider circuit according to claim 1, wherein the pulse generator is configured to select a subgroup including up to two signals out of the M signals based on the control command;

to process the signals of the subgroup by at least one logic gate to produce a signal with a period TP whose duty cycle corresponds to the control command, and to input this signal with the second clock signal to an AND logical gate which produces the second signal.

13. The electronic sub-integer frequency divider circuit according to claim 1, comprising a first-level circuitry which comprises a plurality of logical gates and a multiplexer MX1 which is clocked by the second clock signal;

wherein the first-level circuitry is configured to receive as input one or more of the M signals and to selectively output, based on the control command, each out of a plurality of L possible periodic pulses of different duty cycles and with a period TP.

14. The electronic sub-integer frequency divider circuit according to claim 13, wherein for two of more of the plurality of L possible periodic pulses the multiplexer MX1 is configured to output one of the periodic pulse by selecting, in response to the control command, a signal provided to the multiplexer MX1 by one of the plurality of the logical gates which processes two of the M signals to produce the periodic pulse.

15. The electronic sub-integer frequency divider circuit according to claim 1, wherein:

the electronic sub-integer frequency divider circuit is part of an integrated circuit which further includes an additional unit to which the output signal of the electronic sub-integer frequency divider circuit is provided and which can operate in multiple frequencies;

wherein the electronic sub-integer frequency divider circuit comprises a prescaler circuit having a dividing factor A, which is configured to receive an input signal of the electronic sub-integer frequency divider circuit and to process it to produce the plurality of phase-shifted signals which comprise differential I (in-phase) and Q (quadrature-phase) phase signals, and which is electrically coupled to the phase rotator circuit for providing the phase-shifted signals to the phase-rotator circuit;

wherein the phase rotator circuit is further configured to phase interpolate between the plurality of phase-shifted signals output from the prescaler circuit to generate the plurality of phase-shift states having a minimum phase-shift resolution of Δ

φ

, and is electrically coupled to a post-scaler integer divider having a dividing factor B which is configured to process the first signal to produce the first clock signal;

wherein the post-scaler integer divider is electrically coupled to a conversion circuit which converts the first clock signal to match to requirements of CMOS logic, and which is electrically coupled to;

the pulse generator for providing the first clock signal to the pulse generator, and to a first CMOS integer divider having a dividing factor C, which is configured to process the converted first clock signal to produce the second clock signal;

wherein the first CMOS integer divider is electrically coupled to;

the pulse generator for providing the second clock signal to the pulse generator, and to a second CMOS integer divider having a dividing factor P;

wherein the second CMOS integer divider is configured to process the second clock signal to produce the plurality of M signals and to provide one of the M signals as the output signal of the electronic sub-integer frequency divider circuit;

wherein the second CMOS integer divider is electrically coupled to the pulse generator for providing the plurality of M signals to the pulse generator;

wherein the pulse generator is electrically coupled to a phase rotator controller which is configured to generate, based on the rate of pulses in the regulating signal, control signals for the phase rotator circuit;

wherein the phase rotator circuit is configured to rotatably output the one or more phase-shift states at a rate determined by the control signals, thereby producing a first signal whose frequency is determined by the frequency f_A and by the control signals;

wherein the phase rotator controller is electrically coupled to the phase rotator controller via a second conversion circuit which converts the control signals to match to electrical requirements of the phase-rotator circuit.

16. A phase-locked loop frequency synthesizer, comprising:

a phase detector;

a low pass filter coupled to the output of the phase detector;

a voltage controlled oscillator (VCO) coupled to the output of the low-pass filter;

a fractional frequency divider circuit connected in a feedback loop between an output of the VCO and an input to the phase detector, wherein the fractional frequency divider circuit comprises;

(i) a phase rotator circuit configured to rotatably output, at a rate determined by a rate of pulses in a regulating signal, one or more of a plurality of phase-shift states having a frequency f_A, thereby producing a first signal whose frequency is determined by the frequency f_A and by the regulating signal;

(ii) a clock circuitry configured to process the first signal to produce a first clock signal and a second clock signal which is different from the first clock signal;

(iii) a pulse generator configured to;

(a) receive a plurality of M signals having a period TP and of different phases;

wherein the period TP is longer than the periods of the first and the second clock signals;

(b) based on a control command, to process the second clock signal and one or more of the M signals, to produce a second signal which includes S pulses in each period TP; and

(c) process the second signal and the first clock signal to produce the regulating signal so that it includes Q pulses in each period TP, wherein Q is different from S; and

(iv) an output interface configured to provide a sub-integer output signal whose frequency is responsive to the regulating signal.

17. A method for sub-integer frequency division in electronic circuits, the method comprising:

processing a first signal that is outputted by a phase-rotator circuit to produce a first clock signal and a second clock signal which is different from the first clock signal;

based on a control command, processing the second clock signal and at least one signal having a period TP, thereby producing a second signal which includes S pulses in each period TP;

wherein the period TP is longer than the periods of the first and the second clock signals;

processing the second signal to produce a regulating signal, wherein if a first criterion is fulfilled the producing of the regulating signal comprises producing the regulating signal by processing the second signal and the first clock signal, so that the regulating signal includes Q pulses in each period TP, wherein Q is different from S;

producing the first signal by rotatably outputting from the phase rotator circuit at a rate determined by the regulating signal one or more of a plurality of phase-shift states having a frequency f_A, so that a frequency of the first signal is determined by the frequency f_A and by the regulating signal; and

providing a sub-integer output signal whose frequency is responsive to the regulating signal.

18. The method according to claim 17, comprising processing the first clock signal to produce the second clock signal.

19. The method according to claim 17, wherein the first criterion pertains to content of the control command, wherein the method comprises producing the regulating signal based on the control command so that:

the regulating signal includes Q pulses in each period TP if the control command fulfils the first criterion, and S pulses in each period TP otherwise.

20. The method according to claim 17, comprising producing the regulating signal by processing the second signal and another signal to provide the regulating signal so that Q=S+G, wherein G is a preconfigured fixed number.

21. The method according to claim 20, comprising processing at least the first clock signal to produce a third signal which includes a preconfigured fixed number Y of pulses;

and alternating between the second signal and the third signal to produce the regulating signal.

22. The method according to claim 17, comprising producing the second clock signal from the first clock signal by an integer frequency divider.

23. The method according to claim 17, comprising producing the plurality of M signals from the second clock signal by an integer divider.

24. A pulse generator, comprising:

a first-level circuitry which comprises a plurality of logical gates and a multiplexer which is clocked by a second clock signal;

the first-level circuitry being configured to (a) receive as input one or more of a plurality of M signals having a period TP and of different phases which are provided to the pulse generator, and (b) to selectively output, based on a control command, each out of a plurality of L possible periodic pulses of different duty cycles and with a period TP;

a second-level circuitry being configured to process one or more of the L periodic pulses and the second clock signal, to produce a second signal which includes S pulses in each period TP;

a third-level circuitry being configured to process the second signal and a first clock signal to produce a regulating signal so that it includes Q pulses in each period TP, wherein Q is different from S; and

an electrical coupling for transmitting the regulating signal from the third-level circuitry toward a phase-rotator of an electronic sub-integer frequency divider circuit in which the pulse generator is included, thereby causing the electronic sub-integer frequency divider circuit to operate in a sub-integer division ratio mode;

wherein the first clock signal and the second clock signal which is different from the first clock signal are produced by a processing of a first signal whose frequency is determined by a rate of pulses in the regulating signal and which is outputted by the phase-rotator circuit which rotatably outputs, at a rate determined by the rate of pulses in a regulating signal, one or more of a plurality of phase-shift states having a frequency f_A;

wherein the period TP is longer than the periods of the first and the second clock signals.