Optimization Methods for Amplifier with Variable Supply Power

• US 20140184334A1
• Filed: 03/14/2013
• Published: 07/03/2014
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Nobbe, Dan William, Dykstra, Jeffrey A., Olson, Chris, Cable, James S.
• Granted Patent: US 9,219,445 B2
• Time in Patent Office: Days
• US Class Current: 330/291
• CPC Class Codes: H03D 1/18 of semiconductor devices
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/0216 Continuous control
• CPC Class Codes: H03F 1/0222 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0244 Stepped control
• CPC Class Codes: H03F 1/025 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3282 Acting on the phase and the amplitude of the input signal
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/108 A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
• CPC Class Codes: H03F 2200/129 there being a feedback over the complete amplifier
• CPC Class Codes: H03F 2200/15 the supply or bias voltage or current at the drain side of a FET being continuously controlled by a controlling signal
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/213 A variable capacitor being added in the input circuit, e.g. base, gate, of an amplifier stage
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/387 : A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/408 : the output amplifying stage of an amplifier comprising three power stages
• CPC Class Codes: H03F 2200/411 : the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/451 : the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/534 : Transformer coupled at the input of an amplifier
• CPC Class Codes: H03F 2200/537 : A transformer being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/541 : Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2200/546 : A tunable capacitance being present in an amplifier circuit
• CPC Class Codes: H03F 2200/78 : A comparator being used in a controlling circuit of an amplifier
• CPC Class Codes: H03F 2201/3233 : Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
• CPC Class Codes: H03F 2203/45112 : the biasing of the differential amplifier being controlled from the input or the output signal
• CPC Class Codes: H03F 2203/45366 : the AAC comprising multiple transistors parallel coupled at their gates only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 2203/45544 : the IC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45638 : the LC comprising one or more coils
• CPC Class Codes: H03F 2203/45731 : the LC comprising a transformer
• CPC Class Codes: H03F 3/191 : Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/193 : with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/21 : with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/211 : using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/24 : of transmitter output stages
• CPC Class Codes: H03F 3/45179 : using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages

Abstract

Optimization methods via various circuital arrangements for amplifier with variable supply power are presented. In one embodiment, a switch can be controlled to include or exclude a feedback network in a feedback path to the amplifier to adjust a response of the amplifier dependent on a region of operation of the amplifier arrangement (e.g. linear region or compression region).

Claims

1. A circuit comprising:

an amplifying arrangement configured to operate in a compression region of the amplifying arrangement and/or in a linear region of the amplifying arrangement;

a variable power supply operatively coupled to the amplifying arrangement and adapted to provide a dynamic supply power to the amplifying arrangement; and

an optimizing circuital arrangement operatively coupled to the amplifying arrangement and configured to operatively affect a response of the amplifying arrangement depending on the region of operation of the amplifying arrangement thus impressing a desired effect upon a radio frequency (RF) output of the amplifying arrangement.

2. The circuit according to claim 1, wherein the desired effect impressed upon the RF output of the amplifying arrangement when operating in the linear region and/or in the compression region comprises one or more of:

a) improving output amplitude linearity, b) improving output phase linearity, c) improving output gain, d) reducing output distortion, e) improving output efficiency and f) reducing undesired effects in correspondence of a transition from a linear region of operation to a compression region of operation and vice versa.

3. The circuit according to claim 1 wherein the optimizing circuital arrangement comprises

a feedback path operatively connected between the RF output of the amplifying arrangement and an RF input of the amplifying arrangement, the feedback path comprising a feedback network configured to operatively affect the response of the amplifying arrangement according to a variable value of a first input control signal.

4. The circuit according to claim 3, wherein the feedback network comprises a switch adapted to operatively connect and disconnect the feedback path between the RF output and the RF input based on the value of the first input control signal wherein:

the feedback path is operatively connected when the amplifying arrangement operates in the linear region, and

the feedback path is operatively disconnected when the amplifying arrangement operates in the compression region.

5. The circuit according to claim 4, wherein the feedback network further comprises a resistive-capacitive (R-C) series network operatively connected in series with the switch.

6. The circuit according to claim 3, wherein the feedback network comprises a variable resistor adapted to operatively affect the response of the amplifying arrangement according to the value of the first input control signal wherein:

a resistance value of the variable resistor is varied by the first input control signal within a first range of resistance values when the amplifying arrangement operates in the linear region, and

the resistance value of the variable resistor is varied by the first input control signal within a second range of resistance values when the amplifying arrangement operates in the compression region.

7. The circuit according to claim 6, wherein the resistance value of the variable resistor is:

a) continuously variable, or b) variable in discrete steps.

8. The circuit according to claim 3, wherein the feedback network comprises at least one active device.

9. The circuit according to claim 1, wherein the optimizing circuital arrangement comprises a first tunable matching network operatively coupled to the RF output of the amplifying arrangement such as to affect an output load to the amplifying arrangement in correspondence of an impedance value of the first tunable matching network, said first tunable matching network not included within the feedback path, wherein the impedance value of the first tunable matching network is adjustable based on a variable value of a second input control signal.

10. The circuit according to claim 9, wherein the impedance value of the first tunable matching network is:

a) continuously variable, or b) variable in discrete steps.

11. The circuit according to claim 9, wherein varying the value of the second input control signal in correspondence of the region of operation of the amplifying arrangement operatively modifies the load lines of the amplifying arrangement.

12. The circuit according to claim 1, wherein the optimizing circuital arrangement comprises a second tunable matching network operatively coupled to an RF input of the amplifying arrangement such as to affect an input load to the amplifying arrangement in correspondence of an impedance value of the second tunable matching network, said second tunable matching network not included within the feedback path, wherein the second tunable matching network is adjustable based on a variable value of a third input control signal.

13. The circuit according to claim 12, wherein the impedance value of the first tunable matching network is:

a) continuously variable, or b) variable in discrete steps.

14. The circuit according to claim 12, wherein varying the value of the third input control signal in correspondence of the region of operation of the amplifying arrangement operatively affects the response of the amplifying arrangement.

15. The circuit according to claim 1, wherein the optimizing circuital arrangement comprises one or more of:

a) the optimizing circuital arrangement of the claim 3, b) the optimizing circuital arrangement of claim 9, and c) the optimizing circuital arrangement of claim 12.

16. The circuit according to claim 15, wherein the dynamic supply power is configured to vary as a time varying function of an envelope signal of an RF input signal of the amplifying arrangement.

17. The circuit according to claim 15, wherein the variable values of one or more of:

a) the first input control signal,

b) the second input control signal, and

c) the third input control signal,

are varied in correspondence of the region of operation of the amplifying arrangement, such as to affect the response of the amplifying arrangement by impressing a desired effect upon the output of the amplifying arrangement.

18. The circuit according to claim 17, wherein the desired effect impressed upon the RF output of the amplifying arrangement when operating in the linear region or in the compression region comprises one or more of:

a) improving output amplitude linearity, b) improving output phase linearity, c) improving output gain, d) reducing output distortion, e) improving output efficiency and f) reducing undesired effects in correspondence of a transition from a linear region of operation to a compression region of operation and vice versa.

19. The circuit according to claim 1 or claim 15, wherein the amplifying arrangement further comprises stacked transistors having a plurality of bias terminals configured to operatively provide a plurality of variable bias supplies to a plurality of gates of the stacked transistors, wherein the plurality of variable bias supplies are configured to further affect the response of the amplifying arrangement.

20. The circuit according to claim 19, wherein the variable values of one or more of

a) the first input control signal,

b) the second input control signal,

c) the third input control signal, and

d) one or more of the plurality of variable bias supplies,

are varied in correspondence of the region of operation of the amplifying arrangement, such as to affect the response of the amplifying arrangement by impressing a desired effect upon the output of the amplifying arrangement.

21. The circuit according to claim 19, further comprising a circuital arrangement adapted to provide one or more variable bias supplies from the plurality of variable bias supplies to the one or more gate terminals, wherein the circuital arrangement comprises at least one of:

a) a plurality of resistors configured as a voltage divider network, b) a transceiver unit, c) a variable power supply unit, and d) a lookup table.

22. The circuit according to claim 21, wherein the lookup table comprises current gain characteristic curve data of the stacked transistors.

23. The circuit according to claim 19, wherein one or more of the plurality of variable bias supplies vary as a function of an envelope signal of an RF input signal of the amplifying arrangement.

24. The circuit according to claim 23, wherein one or more of the plurality of variable bias supplies do not vary.

25. The circuit according to claim 19, wherein at least one of the one or more of the plurality of variable bias supplies varies as a function of an envelope signal of the RF input signal when the amplifying arrangement operates in the compression region, and wherein at least one of the one or more of the plurality of variable bias supplies does not vary when the amplifying arrangement operates in the linear region.

26. The circuit according to claim 1 or claim 15, further comprising a circuital arrangement configured to impress an effect upon an RF input signal of the amplifying arrangement such as to compensate for an undesired effect impressed upon the RF output of the amplifying arrangement in correspondence of affecting the response of the amplifying arrangement.

27. The circuit according to claim 26, wherein the effect impressed upon the RF input signal to the amplifying arrangement comprises one or more of:

a) phase pre-distortion and b) amplitude pre-distortion.

28. The circuit according to claim 27, wherein the further circuital arrangement comprises one or more of:

a) a lookup table comprising pre-distortion coefficients, and b) a transceiver unit.

29. The circuit according to claim 28, wherein the pre-distortion coefficients are in correspondence of the undesired effects impressed upon the output of the amplifying arrangement.

30. The circuit according to claim 1, wherein:

the amplifying arrangement comprises a cascaded series-combination of amplifiers;

at least one amplifier of the cascaded series-combination of amplifiers is configured to operate in a compression region of the amplifier and/or in a linear region of the amplifier and is adapted to receive a dynamic supply power from the variable power supply, and

the RF input signal of the amplifying arrangement is operatively coupled to an input of a first amplifier of the cascaded series-combination of amplifiers and the RF output signal of the amplifying arrangement is in correspondence of an output of a last amplifier of the cascaded series-combination of amplifiers.

31. The circuit according to claim 30, wherein the optimizing circuital arrangement comprises one or more of:

a) the optimizing circuital arrangement of the claim 3, b) the optimizing circuital arrangement of claim 9, and c) the optimizing circuital arrangement of claim 12.

32. The circuit according to claim 31 wherein the optimizing circuital arrangement further comprises one or more tunable matching networks, each operatively coupled in a series configuration between an output of an amplifier and an input of a next amplifier of the cascaded series-combination of amplifiers, such as each tunable matching network to affect an output load of the corresponding amplifier.

33. A circuit comprising:

a cascaded series-combination of circuits according to claim 17;

an RF input signal operatively coupled to an input of a first amplifying arrangement of the cascaded series-combination of circuits; and

an RF output signal operatively coupled to an output of a last amplifying arrangement of the cascaded series-combination of circuits, wherein affecting a response of the circuit comprises affecting a response of one or more amplifying arrangements of the cascaded series-combination of circuits.

34. The circuit according to claim 33, wherein one or more of the optimizing circuital arrangements of the cascaded series-combination of circuits comprises one or more of:

a) the optimizing circuital arrangement of claim 3, b) the optimizing circuital arrangement of claim 9, and c) the optimizing circuital arrangement of claim 12.

35. A method for affecting a response of an amplifying arrangement comprising:

providing an amplifying arrangement configured to operate in a linear region or in a compression region of the amplifying arrangement, the amplifying arrangement having an RF input, an RF output and a supply power input terminal operatively configured to receive a dynamic supply power;

providing a tunable circuital arrangement operatively coupled to the amplifying arrangement;

detecting the region of operation of the amplifier based on a provided signal;

generating a control signal as a consequence of detecting the region of operation of the amplifier;

applying the control signal to the tunable circuital arrangement;

tuning the tunable circuital arrangement based on the applied control signal;

affecting the response of the amplifying arrangement in correspondence of the tuning of the circuital arrangement by impressing a desired effect upon the RF output of the amplifying arrangement.

36. The method of claim 35 wherein the circuital arrangement comprises one or more of a) a tunable matching network operatively coupled to the RF input and/or to the RF output signal, and b) a tunable feedback network operatively connected between the RF input and RF output signals.

37. The method of claim 36 wherein affecting the response of the amplifier comprises one or more of:

a) tuning the tunable feedback network in correspondence of the region of operation of the amplifying arrangement, and

b) tuning the tunable matching network in correspondence of the region of operation of the amplifying arrangement.

38. The method of claim 37, wherein affecting the response of the amplifier impresses a desired effect upon the output of the amplifier comprising a) improving output amplitude linearity, b) improving output phase linearity, c) improving output gain, d) reducing output distortion, e) improving output efficiency, f) reducing undesired effects in correspondence of a transition from a linear region of operation to a compression region of operation and vice versa, and g) maintaining a desired gain in correspondence of operation in the compression region and in the linear region.

39. The method of claim 35 wherein the amplifying arrangement further comprises stacked transistors having a plurality of bias terminals configured to operatively provide a plurality of variable bias supplies to a plurality of gates of the stacked transistors, wherein the plurality of variable bias supplies are configured to further affect the response of the amplifying arrangement.

40. The method according to claim 35 wherein operation of the amplifier in the compression region is based on one of:

a) envelope tracking method, b) envelope following method, c) average power tracking method, and d) polar modulation method.