Amplifiers Operating in Envelope Tracking Mode or Non-Envelope Tracking Mode

• US 20140184335A1
• Filed: 03/14/2013
• Published: 07/03/2014
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Nobbe, Dan William, Dykstra, Jeffrey A., Olson, Chris, Cable, James S.
• Granted Patent: US 9,667,195 B2
• Time in Patent Office: Days
• US Class Current: 330/291
• CPC Class Codes: H03D 1/18 of semiconductor devices
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/0216 Continuous control
• CPC Class Codes: H03F 1/0222 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0244 Stepped control
• CPC Class Codes: H03F 1/025 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3282 Acting on the phase and the amplitude of the input signal
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/108 A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
• CPC Class Codes: H03F 2200/129 there being a feedback over the complete amplifier
• CPC Class Codes: H03F 2200/15 the supply or bias voltage or current at the drain side of a FET being continuously controlled by a controlling signal
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/213 A variable capacitor being added in the input circuit, e.g. base, gate, of an amplifier stage
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/387 : A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/408 : the output amplifying stage of an amplifier comprising three power stages
• CPC Class Codes: H03F 2200/411 : the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/451 : the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/534 : Transformer coupled at the input of an amplifier
• CPC Class Codes: H03F 2200/537 : A transformer being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/541 : Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2200/546 : A tunable capacitance being present in an amplifier circuit
• CPC Class Codes: H03F 2200/78 : A comparator being used in a controlling circuit of an amplifier
• CPC Class Codes: H03F 2201/3233 : Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
• CPC Class Codes: H03F 2203/45112 : the biasing of the differential amplifier being controlled from the input or the output signal
• CPC Class Codes: H03F 2203/45366 : the AAC comprising multiple transistors parallel coupled at their gates only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 2203/45544 : the IC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45638 : the LC comprising one or more coils
• CPC Class Codes: H03F 2203/45731 : the LC comprising a transformer
• CPC Class Codes: H03F 3/191 : Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/193 : with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/21 : with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/211 : using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/24 : of transmitter output stages
• CPC Class Codes: H03F 3/45179 : using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages

Abstract

Various envelope tracking amplifiers are presented that can be switched between an ET (envelope tracking) mode and a non-ET mode. Switches and/or tunable components are utilized in constructing the envelope tracking amplifiers that can be switched between the ET mode and the non-ET mode.

Claims

1. An amplifier arrangement configured to operate based on a mode of operation, comprising:

an adjustable power supply controlled by a first control signal to provide either a variable supply or a constant supply to the amplifier arrangement; and

a power amplifier comprising a configuration arrangement controlled by secondary control signals, the configuration arrangement adapted to configure the power amplifier based on the mode of operation,

wherein the mode of operation comprises a first mode of operation and a second mode of operation, the first mode of operation corresponding to the adjustable power supply providing variable supply to the power amplifier, the second mode of operation corresponding to the adjustable power supply providing constant supply to the power amplifier, the mode of operation switching between the first mode of operation and the second mode of operation and vice versa based on an input signal to the power amplifier.

2. The amplifier arrangement according to claim 1, wherein the adjustable power supply is adapted to provide bias voltages to the power amplifier, the bias voltages used to bias a drain and/or one or more gates of the power amplifier.

3. The amplifier arrangement according to claim 1 further comprising:

a constant power supply, and

a supply switch adapted to select between the constant power supply and the adjustable power supply to bias the power amplifier, the supply switch controlled by the secondary control signals based on the mode of operation.

4. The amplifier arrangement according to claim 3, wherein the adjustable power supply is configured to provide constant supply to bias the drain of the power amplifier when the supply switch selects the constant power supply.

5. The amplifier arrangement according to claim 1, further comprising one or more tunable matching networks, the one or more tunable matching networks connected to the input and/or output of the amplifier arrangement to provide a desired matching based on the mode of operation.

6. The amplifier arrangement according to claim 5, wherein the desired matching is tuned as a function of an envelope signal when the adjustable power supply provides variable supply to the power amplifier.

7. The amplifier arrangement according to claim 1, further comprising a feedback loop, the feedback loop is connected between an input and an output of the amplifier arrangement and is adapted to adjust an amplitude and/or a phase response of the amplifier arrangement based on the mode of operation.

8. The amplifier arrangement according to claim 7, wherein the feedback loop comprises a resistor, a capacitor and a feedback loop switch, the feedback loop switch adapted to enable/disable an operation of the feedback loop with respect to the amplifier arrangement and is controlled by secondary control signals based on the mode of operation.

9. The amplifier arrangement according to claim 7, wherein the feedback loop comprises a tunable resistor and a tunable capacitor, the tunable resistor and the tunable capacitor adapted to tune the feedback loop with respect to the amplifier arrangement and controlled by secondary control signals based on the mode of operation.

10. The amplifier arrangement according to claim 2, wherein the bias voltages to the one or more gates of the power amplifier is provided from an external power supply.

11. The amplifier arrangement according to claim 2, further comprising one or more voltage divider resistors in series connection with the adjustable power supply, the one or more voltage divider resistors adapted to generate a proportioned bias voltage to one or more gates of the power amplifier.

12. The amplifier arrangement according to claim 2, further comprising one or more bias terminal supply switches, wherein the bias terminal supply switches are connected to one or more gate bias terminals of the power amplifier and are adapted to select between providing one or more gate bias terminals with bias voltages from either an external power supply or the adjustable power supply, the one or more bias terminal supply switches controllable by secondary control signals based on the mode of operation.

13. The amplifier arrangement according to claim 2, wherein the amplifier arrangement further comprises:

an envelope detector operative to receive an input RF signal and configured to provide as an output an envelope signal corresponding to an envelope of the input RF signal; and

a control unit connected with the envelope detector, the control unit operative to receive the envelope signal from the envelope detector and configured to generate the first control signal.

14. The amplifier arrangement according to claim 13, wherein the control unit is further configured to provide secondary control signals to the power amplifier, wherein the secondary control signal further configures the power amplifier through the configuring arrangement based on the mode of operation.

15. The amplifier arrangement according to claim 13, wherein a secondary control signal is provided to the amplifier arrangement not by the control unit.

16. The amplifier arrangement according to claim 15, wherein the secondary control signal is provided to the amplifier arrangement from a transceiver.

17. The amplifier arrangement according to claim 14, wherein the configuring arrangement comprises switches and/or tunable elements used to configure the operation of the power amplifier based on the mode of operation.

18. The amplifier arrangement according to claim 2 further comprising a second plurality of stacked FET transistors, wherein the second plurality of stacked FET transistors comprises a number of stacked FET transistors different from a first plurality of stacked FET transistors of the power amplifier;

and

a stack switch connected to the adjustable power supply and operative to select between the first plurality of stacked FET transistors or the second plurality of stacked FET transistors, the stack switch is controlled by secondary control signals based on the mode of operation.

19. A circuital arrangement comprising:

the amplifier arrangement of claim 1;

one or more additional amplifiers to further amplify an input RF signal; and

one or more bypass switches adapted to include/exclude the one or more additional amplifiers from the circuital arrangement with respect to the amplifier arrangement, wherein the one or more bypass switches are controlled by secondary control signals based on the mode of operation.

20. A circuital arrangement comprising:

the amplifier arrangement of claim 1;

one or more additional power amplifiers adapted to further amplify an input RF signal provided on one or more separate paths, the one or more separate paths each providing a different amplification level for the input RF signal; and

one or more path switches, the one or more path switches adapted to select one particular path to provide an amplified input RF signal to an output port of the arrangement, the one or more path switches being controlled by secondary control signals based on a desired mode of operation.

43. The circuital arrangement of claim 20, wherein the desired mode of operation is based on one of:

a) a power level of the input signal, and b) a desired amplification level of the input signal.

44. The circuital arrangement of claim 43 comprising two separate paths, wherein a first power amplifier in correspondence of a first path of the two separate paths is configured to operate in the first mode of operation and a second power amplifier in correspondence of a second path of the two separate paths is configured to operate in the second mode of operation.

46. The amplifier arrangement according to claim 14, wherein the configuring arrangement is adapted to perform one or more of:

a) configuring a bias voltage to a gate of at least one of the one or more gates, and b) activating and/or deactivating at least one of a plurality of stacked FET transistors of the power amplifier.

47. The amplifier arrangement of claim 4, wherein the mode of operation is based on a combination of:

a) a power consumption of the adjustable power supply, b) a power level of an input signal to the amplifier arrangement, and c) a power level of an output signal of the amplifier arrangement.

48. The amplifier according to any one of claims 1, 2, 3, 5, 7, 10, 11, 12, 13, 18 or 20, wherein the first mode of operation comprises one of:

a) envelope tracking, b) envelope following, c) average power tracking, and d) polar modulation.

49. The amplifier arrangement according to claim 17, wherein the tunable elements comprise at least one tunable capacitor and one tunable resistor operatively connected to a gate of the one or more gates of the power amplifier, the tunable capacitor being connected between the gate and a reference voltage, and the tunable resistor being series connected between the gate and a corresponding bias voltage terminal.

50. The amplifier arrangement according to claim 49, wherein tuning of a tunable element comprises one of:

a) continuously varying a value of the tunable element, and b) varying in discrete steps the value of the tunable element.

51. The amplifier arrangement according to claim 49, wherein the tunable capacitor is configured to perform any combination of:

a) optimize a bias voltage across the gate for a desired mode of operation of the power amplifier, b) optimize an envelope signal voltage across the gate for a desired mode of operation of the power amplifier, and c) optimize an RF voltage swing across the gate for a desired mode of operation of the power amplifier.

21. A method for configuring an amplifier arrangement to operate based on a mode of operation comprising:

providing an adjustable power supply adapted to provide either variable supply or constant supply to the amplifier arrangement;

providing a first control signal to control the adjustable power supply, wherein the first control signal controls which supply to be provided to the amplifier arrangement;

providing a power amplifier adapted to amplify an input signal, the power amplifier further comprising a configuration arrangement adapted to configure the power amplifier based on the mode of operation; and

providing a second control signal to control the configuration arrangement,

wherein the mode of operation comprises a first mode of operation and a second mode of operation, the first mode of operation corresponding to the adjustable power supply providing variable supply to the power amplifier, the second mode of operation corresponding to the adjustable power supply providing constant supply to the power amplifier, the mode of operation switching between the first mode of operation and the second mode of operation and vice versa based on the first control signal and the second control signal.

22. The method according to claim 21, wherein the adjustable power supply is adapted to provide bias voltages to the power amplifier, the bias voltages used to bias a drain and/or one or more gates of the power amplifier.

23. A method according to claim 21 further comprising:

providing a constant power supply; and

providing a supply switch, wherein the supply switch is adapted to select between the constant power supply and the adjustable power supply to bias one or more gates of the power amplifier, the supply switch controlled by the secondary control signals based on the mode of operation.

24. The method according to claim 23, wherein the adjustable power supply is configured to provide constant supply to bias the drain of the power amplifier when the supply switch selects the constant power supply.

25. The method according to claim 21, further comprising:

providing one or more tunable matching networks, wherein the one or more tunable matching networks connected to the input and/or output of the amplifier arrangement are used to provide a desired matching based on the mode of operation.

26. The method according to claim 25, wherein the desired matching is tuned as a function of an envelope signal when the adjustable power supply provides variable supply to the power amplifier.

27. The method according to claim 21, further comprising:

providing a feedback loop, wherein the feedback loop is connected between an input and an output of the amplifier arrangement and is adapted to adjust an amplitude and/or a phase response of the amplifier arrangement based on the mode of operation.

28. The method according to claim 27, wherein the feedback loop comprises a resistor, a capacitor and a feedback loop switch, the feedback loop switch adapted to enable or disable an operation of the feedback loop with respect to the amplifier arrangement and is controlled by secondary control signals based on the mode of operation.

29. The method according to claim 27, wherein the feedback loop comprises a tunable resistor and a tunable capacitor, the tunable resistor and the tunable capacitor adapted to tune the feedback loop with respect to the amplifier arrangement and controlled by secondary control signals based on the mode of operation.

30. The method according to claim 22, wherein the bias voltages to the one or more gates of the power amplifier is provided from an external power supply.

31. The method according to claim 22, further comprising:

providing one or more voltage divider resistors in series connection with the adjustable power supply, wherein the one or more voltage divider resistors are adapted to generate a proportioned bias voltage to one or more gates of the power amplifier.

32. The method according to claim 22, further comprising:

providing one or more bias terminal supply switches, wherein the bias terminal supply switches are connected to one or more gate bias terminals of the power amplifier and are adapted to select between providing one or more gate bias terminals with bias voltages from either an external power supply or the adjustable power supply, the one or more bias terminal supply switches controllable by secondary control signals based on the mode of operation.

33. The method according to claim 22, further comprising:

providing an envelope detector operative to receive an input signal and configured to provide as an output an envelope signal corresponding to an envelope of the input signal; and

providing a control unit connected with the envelope detector, the control unit operative to receive the envelope signal from the envelope detector and configured to generate the first control signal.

34. The method according to claim 33, wherein the control unit is further configured to provide secondary signals to the power amplifier, wherein the secondary control signal configures the power amplifier through the configuring arrangement based on the mode of operation.

35. The method according to claim 33, wherein the secondary control signal is provided to the amplifier arrangement not by the control unit.

36. The method according to claim 35, wherein the secondary control signal is provided to the amplifier arrangement from a transceiver.

37. The method according to claim 34, wherein the configuring arrangement comprises switches and/or tunable elements used to configure the operation of the power amplifier based on the mode of operation.

38. The method according to claim 21, further comprising:

providing a second plurality of stacked FET transistors, wherein the second plurality of stacked FET transistors comprises a number of stacked FET transistors different from a first plurality of stacked FET transistors of the power amplifier; and

providing a stack switch connected to the adjustable power supply and operative to select between the first plurality of stacked FET transistors or the second plurality of stacked FET transistors, the stack switch is controlled by secondary control signals based on the mode of operation.

39. A method comprising:

using the method of claim 21;

providing one or more additional amplifiers to further amplify an input signal; and

providing one or more bypass switches adapted to include or exclude the one or more additional amplifiers with respect to the amplifier arrangement, wherein the one or more bypass switches are controlled by secondary control signals based on the mode of operation.

40. A method comprising:

using the method of claim 21;

providing one or more additional amplifiers adapted to further amplify an input signal provided on one or more separate paths, wherein the one or more separate paths each provide a different amplification level for the input signal; and

providing one or more path switches, the one or more path switches adapted to select one particular path and are controlled by secondary control signals based on the mode of operation.

41. The method according to claim 21, wherein the mode of operation selected by the first and the second control signals is based on one of:

a) a power level of the input signal, and b) a desired amplification level of the input signal.

42. The method according to claim 40, wherein the mode of operation is based on one of:

a) a power level of the input signal, and b) a desired amplification level of the input signal.

45. The method according to claim 34, wherein the configuring arrangement is adapted to perform one or more of:

a) configuring a bias voltage to a gate of at least one of the one or more gates of the power amplifier, and b) activating and/or deactivating at least one of a plurality of stacked FET transistors of the power amplifier.

52. The method according to claim 37, wherein the tunable elements comprise at least one tunable capacitor and one tunable resistor operatively connected to a gate of the one or more gates of the power amplifier, the tunable capacitor being connected between the gate and a reference voltage, and the tunable resistor being series connected between the gate and a corresponding bias voltage terminal.

53. The method according to claim 52, wherein tuning of a tunable element comprises one of:

a) continuously varying a value of the tunable element, and b) varying in discrete steps the value of the tunable element.

54. The method according to claim 52, wherein the tunable capacitor is configured to perform any combination of:

a) optimize a bias voltage across the gate for a desired mode of operation of the power amplifier, b) optimize an envelope signal voltage across the gate for a desired mode of operation of the power amplifier, and c) optimize an RF voltage swing across the gate for a desired mode of operation of the power amplifier.