Amplifier Dynamic Bias Adjustment for Envelope Tracking

• US 20140184336A1
• Filed: 03/14/2013
• Published: 07/03/2014
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Nobbe, Dan William, Dykstra, Jeffrey A., Olson, Chris, Cable, James S.
• Granted Patent: US 9,413,298 B2
• Time in Patent Office: Days
• US Class Current: 330/296
• CPC Class Codes: H03D 1/18 of semiconductor devices
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/0216 Continuous control
• CPC Class Codes: H03F 1/0222 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0244 Stepped control
• CPC Class Codes: H03F 1/025 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3282 Acting on the phase and the amplitude of the input signal
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/108 A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
• CPC Class Codes: H03F 2200/129 there being a feedback over the complete amplifier
• CPC Class Codes: H03F 2200/15 the supply or bias voltage or current at the drain side of a FET being continuously controlled by a controlling signal
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/213 A variable capacitor being added in the input circuit, e.g. base, gate, of an amplifier stage
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/387 : A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/408 : the output amplifying stage of an amplifier comprising three power stages
• CPC Class Codes: H03F 2200/411 : the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/451 : the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/534 : Transformer coupled at the input of an amplifier
• CPC Class Codes: H03F 2200/537 : A transformer being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/541 : Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2200/546 : A tunable capacitance being present in an amplifier circuit
• CPC Class Codes: H03F 2200/78 : A comparator being used in a controlling circuit of an amplifier
• CPC Class Codes: H03F 2201/3233 : Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
• CPC Class Codes: H03F 2203/45112 : the biasing of the differential amplifier being controlled from the input or the output signal
• CPC Class Codes: H03F 2203/45366 : the AAC comprising multiple transistors parallel coupled at their gates only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 2203/45544 : the IC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45638 : the LC comprising one or more coils
• CPC Class Codes: H03F 2203/45731 : the LC comprising a transformer
• CPC Class Codes: H03F 3/191 : Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/193 : with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/21 : with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/211 : using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/24 : of transmitter output stages
• CPC Class Codes: H03F 3/45179 : using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages

Abstract

An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor.

Claims

1. A circuital arrangement comprising:

an amplifier comprising;

stacked transistors having a plurality of bias terminals configured to operatively provide a plurality of dynamic bias voltages or currents to the stacked transistors;

an input port operatively connected to an input transistor of the stacked transistors;

an output port operatively connected to an output transistor of the stacked transistors; and

a reference terminal operatively coupling the input transistor to a reference potential, wherein the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to the output transistor.

2. The arrangement according to claim 1, wherein the plurality of bias terminals comprise gate terminals of the stacked transistors and a drain terminal of the output transistor from the second subset wherein the drain terminal is operatively connected to the variable output supply bias voltage or current.

3. The arrangement according to claim 2, wherein the input port of the amplifier is operatively coupled to the gate terminal of the input transistor and the output port of the amplifier is operatively coupled to the drain terminal of the output transistor.

4. The arrangement according to claim 3, further comprising a variable voltage or current source operatively coupled to the arrangement and configured to output one or more variable voltages or currents according to a control signal applied to the variable voltage or current source.

5. The arrangement according to claim 4, wherein the control signal is a function of an envelope signal of an input signal to the amplifier, such as the applying of the control signal impresses said function upon the one or more variable voltages or currents output by the variable voltage or current source.

6. The arrangement according to claim 5, wherein the amplifier is configured to operate in at least one of:

a) linear region, b) compression region, or c) switching between compression and linear regions.

7. The arrangement according to claim 6, wherein the dynamic bias voltages or currents are operatively generated from a first variable voltage or current of the one or more variable voltages or currents and the variable output supply bias voltage or current is operatively generated from a second variable voltage or current of the one or more variable voltages or currents.

8. The arrangement according to claim 7, further comprising one or more capacitors connected between the gate terminals of the one or more transistors of the second subset and the ground.

9. The arrangement according to claim 8, wherein the one or more capacitors are configured to perform any combination of:

a) optimize a bias voltage across each of the one or more transistors for a desired operation of the amplifier, b) optimize an envelope signal voltage across each of the one or more transistors for a desired operation of the amplifier, and c) optimize an RF voltage swing across each of the one or more transistors for a desired operation of the amplifier.

10. The arrangement according to claim 8, further comprising one or more resistors connected in series between the gate terminals of the one more transistors of the second subset and the provided plurality of dynamic bias voltages or currents.

11. The arrangement according to claim 7 further comprising a circuital arrangement connected in series between at least one gate terminal of the one or more transistors of the second subset and the provided plurality of dynamic bias voltages or currents, the circuital arrangement comprising at least one active device.

12. The arrangement according to claim 11, wherein the circuital arrangement is configured to operate in a frequency range spanning from DC to a frequency content of the input signal.

13. The arrangement according to claim 10 or claim 12, further comprising a plurality of resistors, the plurality of resistors being configured as a voltage divider to provide the dynamic bias voltages or currents to the gate terminals of the one or more transistors from the second subset based on the first variable voltage or current.

14. The arrangement according to claim 10 or claim 12, wherein at least one of the plurality of the dynamic bias voltages or currents is generated from the first variable voltage or current using a gate modifier function, wherein the gate modifier function comprises at least one of:

a) a scaling function, b) an amplitude shifting function, c) a phase shifting function, and d) an inverting function.

15. The arrangement according to claim 14 further comprising a gate modifier circuital arrangement to generate said gate modifier function, wherein the gate modifier circuital arrangement comprises at least one of:

a) a resistive-inductive-capacitive (RLC) network, b) a current mirror, c) one or more operational amplifiers, and d) one or more digital integrated circuits.

16. The arrangement according to claim 15, wherein the first variable voltage or current is different from the second variable voltage or current.

17. The arrangement according to claim 15, wherein the first variable voltage or current is the same as the second variable voltage or current.

18. The arrangement according to claim 16, wherein the gate terminal of the input transistor is adapted to receive a bias input gate voltage or current which is not generated from the first or the second variable voltage or current.

19. The arrangement according to claim 17, wherein the gate terminal of the input transistor is adapted to receive a bias input gate voltage or current which is not generated from the first or the second variable voltage or current.

20. The arrangement according to claim 7, wherein the gate terminal of the input transistor is adapted to receive a bias input gate voltage or current which is not generated from the first or the second variable voltage or current.

21. The arrangement according to claim 7, further comprising an inductor configured as a choke operatively connected between the output transistor and the variable output supply bias voltage or current provided to the output transistor.

22. The arrangement according to claim 7, wherein the variable voltage or current source is a DC-DC converter.

23. The arrangement according to claim 7, wherein the variable voltage or current source is a DC-DC converter and a linear regulator operatively connected in parallel or in series with each other.

24. The arrangement according to claim 7, wherein the variable voltage or current source is operatively coupled to the drain terminal of the output transistor and is adapted to vary a voltage of the variable output supply bias voltage or current.

25. The arrangement according to claim 7, wherein the variable voltage or current source is operatively coupled to a source terminal of the input transistor and is adapted to vary a current of the variable output supply bias voltage or current.

26. The arrangement according to claim 7, wherein a direct current (DC) component of an at least one of the plurality of the dynamic bias voltages or currents is not operatively generated from the first variable voltage or current.

27. The arrangement according to claim 7, wherein the stacked transistors are configured in a cascode configuration.

28. The arrangement according to claim 7, wherein the stacked transistors are configured in a differential cascode configuration and further comprise differential input and output ports operatively coupled to differential pairs of input and output transistors of the differential cascode configuration.

29. The arrangement according to claim 7, wherein the amplifier is a driver or a final stage amplifier.

30. The arrangement according to claim 7, wherein the reference potential is one of a) a reference ground, b) a virtual ground, and c) an RF ground.

31. The arrangement according to claim 7, wherein the stacked transistors are field effect transistors (FETs) or bipolar junction transistors (BJTs).

32. The arrangement according to claim 7 wherein the amplifier is configured to amplify an input signal with a frequency content above 100 MHz provided at the input port of the amplifier, and reproduce an amplified output signal at the output port of the amplifier, wherein a measured power of the amplified output signal into an output load is above 50 mW.

33. The arrangement according to claim 7 wherein the amplifier is configured to amplify an input signal with a frequency content below 100 MHz provided at the input port of the amplifier, and reproduce an amplified output signal at the output port of the amplifier, wherein a measured power of the amplified output signal into an output load is above 50 mW.

34. The arrangement according to claim 1 or claim 7, wherein the stacked transistors comprise one of:

a) three transistors, b) four transistors, c) five transistors, and d) more than five transistors in a stacked configuration.

35. The arrangement according to claim 3, wherein the variable output supply bias voltage or current is operatively generated from an envelope signal of an input signal.

36. The arrangement according to claim 3, wherein at least one of the plurality of the dynamic bias voltages or currents is operatively generated using an arbitrary function.

37. The arrangement according to claim 35, wherein at least one of the plurality of the dynamic bias voltages or currents is operatively generated from the envelope signal of the input signal using a gate modifier function, wherein the gate modifier function comprises at least one of a) a scaling function, b) an amplitude shifting function, c) a phase shifting function, and d) an inverting function.

38. The arrangement according to claim 35, wherein at least one of the plurality of the dynamic bias voltages or currents is operatively generated from the variable output supply bias voltage or current using a gate modifier function, wherein the gate modifier function comprises at least one of:

a) a scaling function, b) an amplitude shifting function, c) a phase shifting function, and d) an inverting function.

39. The arrangement according to claim 37 further comprising a gate modifier circuital arrangement to generate said gate modifier function, wherein the gate modifier circuital arrangement comprises at least one of:

a) a resistive-inductive-capacitive (RLC) network, b) a current mirror, c) one or more operational amplifiers, and d) one or more digital integrated circuits.

40. The arrangement according to claim 38 further comprising a gate modifier circuital arrangement to generate said gate modifier function, wherein the gate modifier circuital arrangement comprises at least one of a) a resistive-inductive-capacitive (RLC) network, b) a current mirror, c) one or more operational amplifiers, and d) one or more digital integrated circuits.

41. The arrangement according to claim 37, wherein phase shifting of at least one of the plurality of the dynamic bias voltages or currents is used as a pre-distortion operation of an at least one corresponding transistor of the stacked transistors such as to compensate for unintended effects of providing the variable output drain voltage or current to the output transistor.

42. The arrangement according to claim 38, wherein phase shifting of at least one of the plurality of the dynamic bias voltages or currents is used as a pre-distortion operation of an at least one corresponding transistor of the stacked transistors such as to compensate for unintended effects of providing the variable output drain voltage or current to the output transistor.

43. The arrangement according to claim 39 or claim 40, wherein generating of the gate modifier function for the input transistor comprises a current mirror.

44. A circuital arrangement comprising:

an amplifier comprising;

a plurality of transistors comprising an input terminal, an output terminal and a reference terminal;

a variable supply power operatively coupled to the output terminals of the plurality of transistors;

a plurality of transformers each comprising a primary winding and a secondary winding, wherein the primary windings of the transformers are serially connected between the output terminals of the plurality of transistors and the variable supply power;

a reference potential operatively coupled to the reference terminals of the plurality of transistors;

a bias terminal operatively connected to the plurality of transistors and configured to provide a dynamic bias voltage or current to the plurality of transistors;

an input port operatively connected to the input terminals of the plurality of transistors, wherein the input port is configured to provide an RF input signal to the plurality of transistors; and

an output port in correspondence of a secondary winding of a first transformer of the plurality of transformers,

wherein;

the secondary windings of the plurality of transformers are connected in a series arrangement between the output port and the reference potential such that an RF output power provided at the output port in correspondence of the RF input signal is a combination of powers in correspondence of the plurality of secondary windings.

45. The arrangement according to claim 44, wherein at least one of the plurality of transistors is a stack comprising a plurality of transistors.

46. The arrangement according to claim 45, wherein the stack is configured in a cascode configuration.

47. The arrangement according to claim 46, wherein each of the plurality of transistors is a stack comprising a plurality of transistors configured in a cascode configuration.

48. The arrangement according to claim 47, wherein each of the stacks is configured in a differential cascode configuration and further comprises differential input and output terminals operatively coupled to differential pairs of input and output transistors of the differential cascode configuration.

49. The arrangement according to claim 48 further comprising a plurality of differential bias terminals operatively coupled to a plurality of differential pairs of transistors of the differential cascode configuration and configured to provide a plurality of dynamic differential bias voltage to the plurality of differential pairs of transistors.

50. The arrangement according to claim 44, wherein the dynamic bias voltage or current vary as a function of an envelope signal of the RF input signal.

51. The arrangement according to claim 49, wherein at least one of the plurality of the dynamic differential bias voltage varies as a function of an envelope signal of the RF input signal.

52. The arrangement according to claim 49, wherein at least one of the plurality of the dynamic differential bias voltages is operatively generated using an arbitrary function.

64. The arrangement according to any one of claims 44, 53 or 59 wherein each transistor from the stacked transistors and/or plurality of transistors comprises a stacked arrangement of transistors configured in a cascode configuration.

65. The arrangement according to any one claims 44, 53 or 59 wherein the stacked transistors and/or plurality of transistors are configured to operate in a differential input/output configuration.

66. The arrangement according to claim 65, further comprising a plurality of differential bias terminals operatively coupled to a plurality of differential pairs of transistors of the differential cascode configuration and configured to provide a plurality of dynamic differential bias voltage to the plurality of differential pairs of transistors.

67. The arrangement according to claim 66, wherein at least one of the plurality of the dynamic differential bias voltage varies as a function of an envelope signal of the RF input signal.

68. The arrangement according to claim 66, wherein at least one of the plurality of the dynamic differential bias voltages is operatively generated using an arbitrary function.

53. A circuital arrangement comprising:

an amplifier comprising;

stacked transistors having a plurality of bias terminals configured to operatively provide a plurality of dynamic bias voltages or currents to the stacked transistors;

a plurality of transformers operatively coupling an RF input signal provided to an input port of the amplifier, to an input of the transistors from the stacked transistors;

an output port of the amplifier operatively connected to an output transistor of the stacked transistors; and

a last transistor of the stacked transistors being coupled to a reference potential,

wherein the stacked transistors are operatively arranged in series arrangement between a variable output supply bias operatively connected to the output transistor, and the reference potential provided to the last transistor.

54. The arrangement according to claim 53, wherein one or more of the plurality of dynamic bias voltages or currents vary as a function of an envelope signal of the RF input signal.

55. The arrangement according to claim 53 or 54, wherein the variable output supply bias varies as a function of an envelope signal of the RF input signal.

56. The arrangement according to claim 54 further comprising a plurality of capacitors in correspondence to the plurality of dynamic bias voltages and adapted to maintain a bias voltage across a transistor from the stacked transistors.

57. The arrangement according to claim 56, wherein the bias voltage is configured to perform any combination of:

a) optimize a bias voltage across the transistor for a desired operation of the amplifier, b) optimize an envelope signal voltage across the transistor for a desired operation of the amplifier, and c) optimize an RF voltage swing across the transistor for a desired operation of the amplifier.

58. The arrangement according to claim 54, wherein the stacked transistors comprise one of:

a) three transistors, b) four transistors, c) five transistors, and d) more than five transistors in a stacked configuration.

59. A circuital arrangement comprising:

an amplifier comprising;

stacked transistors comprising P-type MOSFET and N-type MOSFET devices operatively arranged in a series arrangement wherein a first half of the stack comprises P-type devices only, and a second half of the stack comprises N-type devices only;

a plurality of bias terminals configured to operatively provide a plurality of dynamic bias voltages or currents to the stacked transistors;

a first terminal operatively coupled to a last N-type device of the stacked transistors and configured to receive a first output supply bias, wherein the last N-type device is at the bottom of the stacked transistors;

a second terminal operatively coupled to a first P-type device of the stacked transistors and configured to receive a second output supply bias, wherein the first P-type device is at the top of the stacked transistors;

an input port operatively coupled to a common input connection in correspondence of the first P-type device and the last N-type device and configured to provide an RF input signal to the stacked transistors, and

an output port of the amplifier operatively coupled to a common output connection of a middle pair of N-type and P-type devices and configured to provide an RF output signal in correspondence of the RF input signal.

60. The arrangement according to claim 59 wherein the first output supply bias is fixed at a reference potential and the second output supply bias is variable.

61. The arrangement according to claim 59 wherein the first output supply bias is variable and the second output supply bias is fixed at a reference potential.

62. The arrangement according to claim 59, wherein one or more of the plurality of dynamic bias voltages or currents vary as a function of an envelope signal of the RF input signal.

63. The arrangement according to claim 60, wherein the stacked transistors comprise one of:

a) two transistors, b) four transistors, c) six transistors, and d) more than six transistors in a stacked configuration.

69. A method of amplifying a signal in a circuital arrangement, the method comprising:

providing an amplifier comprising stacked transistors in a cascode configuration;

adapting the arrangement to operatively connect a plurality of bias supplies to a plurality of gate terminals in correspondence of the stacked transistors and to a drain terminal in correspondence of a drain of an output transistor of the stacked transistors;

applying an input signal to an input port of the arrangement operatively connected to an input transistor of the stacked transistors;

varying the bias supply in correspondence of the drain of the output transistor, and

impressing a desired amplification on the input signal to obtain an amplified output signal by varying at least one bias supply of the plurality of bias supplies in correspondence of the gate terminals.

70. The method of claim 69, wherein varying the bias supply in correspondence of the drain of the output transistor is based on an envelope signal of the input signal applied to the input port of the arrangement.

71. The method of claim 69, wherein varying the bias supply comprises applying to a gate terminal in correspondence of the bias supply a signal obtained by applying at least one of:

a) a scaling function, b) an amplitude shifting function, c) a phase shifting function, and d) an inverting function, to an envelope signal of the input signal.

72. The method of claim 71, wherein the scaling, amplitude shifting, phase shifting or inverting functions are implemented using at least one of:

a) RLC networks, b) circuital arrangements including op-amps, or c) circuital arrangements including digital ICs.