Control Systems and Methods for Power Amplifiers Operating in Envelope Tracking Mode

• US 20140184337A1
• Filed: 03/14/2013
• Published: 07/03/2014
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Nobbe, Dan William, Dykstra, Jeffrey A., Olson, Chris, Cable, James S.
• Granted Patent: US 9,287,829 B2
• Time in Patent Office: Days
• US Class Current: 330/296
• CPC Class Codes: H03D 1/18 of semiconductor devices
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/0216 Continuous control
• CPC Class Codes: H03F 1/0222 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0244 Stepped control
• CPC Class Codes: H03F 1/025 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3282 Acting on the phase and the amplitude of the input signal
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/108 A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
• CPC Class Codes: H03F 2200/129 there being a feedback over the complete amplifier
• CPC Class Codes: H03F 2200/15 the supply or bias voltage or current at the drain side of a FET being continuously controlled by a controlling signal
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/213 A variable capacitor being added in the input circuit, e.g. base, gate, of an amplifier stage
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/387 : A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/408 : the output amplifying stage of an amplifier comprising three power stages
• CPC Class Codes: H03F 2200/411 : the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/451 : the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/534 : Transformer coupled at the input of an amplifier
• CPC Class Codes: H03F 2200/537 : A transformer being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/541 : Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2200/546 : A tunable capacitance being present in an amplifier circuit
• CPC Class Codes: H03F 2200/78 : A comparator being used in a controlling circuit of an amplifier
• CPC Class Codes: H03F 2201/3233 : Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
• CPC Class Codes: H03F 2203/45112 : the biasing of the differential amplifier being controlled from the input or the output signal
• CPC Class Codes: H03F 2203/45366 : the AAC comprising multiple transistors parallel coupled at their gates only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 2203/45544 : the IC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45638 : the LC comprising one or more coils
• CPC Class Codes: H03F 2203/45731 : the LC comprising a transformer
• CPC Class Codes: H03F 3/191 : Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/193 : with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/21 : with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/211 : using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/24 : of transmitter output stages
• CPC Class Codes: H03F 3/45179 : using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages

Abstract

Control systems and methods for power amplifiers operating in envelope tracking mode are presented. A set of corresponding functions and modules are described and various possible system configurations using such functions and modules are presented.

Claims

1. A system for affecting operation of an envelope tracking (ET) amplifier, comprising:

an ET amplifier configured to receive an RF input signal and generate therefrom, an RF output signal based on a response of the ET amplifier; and

a set of operating parameters defining the response of the ET amplifier;

a control circuit adapted to detect an envelope of the RF input signal and generate based on said envelope signal a set of input-control signals that is provided to the ET amplifier for affecting the response according to the set of operating parameters.

2. The system of claim 1, wherein the set of operating parameters comprises of at least one of:

a) maximizing linearity, b) maximizing efficiency, c) minimizing adjacent channel leakage ratio (ACLR), d) minimizing memory effects and e) adjusting output power level.

3. The system of claim 2 wherein the ET amplifier further comprises an amplifier unit wherein the amplifier unit comprises a plurality of stacked transistors operatively coupled to a plurality of bias terminals adapted to receive the set of input-control signals.

4. The system of claim 3 wherein the plurality of bias terminals comprise a plurality of gate terminals of the plurality of stacked transistors and a drain terminal of an output transistor of the amplifier unit.

5. The system of claim 4 wherein the set of input-control signals comprise a plurality of gate-input-control signals and a drain-input-control signal, such as the plurality of gate-input-control signals are provided to the plurality of gate terminals, and the drain-input-control signal is provided to the drain terminal.

6. The system of claim 5 wherein the control circuit further comprises:

an envelope detection circuit adapted to detect the envelope of the RF input signal and generate a corresponding envelope signal;

a waveform generation circuit configured to receive the envelope signal and adapted to generate a set of waveform signals based on the envelope signal and the set of operating parameters, and

an input generation circuit configured to receive the set of waveform signals and adapted to output therefrom the set of input-control signals.

7. The system of claim 6 wherein the waveform generation circuit further comprises:

a gate-waveform generation circuit configured to receive the envelope signal and adapted to generate a set of gate-waveform signals based on the envelope signal and the set of operating parameters, and

a drain-waveform generation circuit configured to receive the envelope signal and adapted to generate a drain-waveform signal based on the envelope signal and the set of operating parameters.

8. The system of claim 7 wherein the input generation circuit further comprises:

a gate-input generation circuit configured to receive the set of gate-waveform signals and adapted to generate therefrom the plurality of gate-input-control signals, and

a drain-input generation circuit configured to receive the drain-waveform signal and adapted to generate therefrom the drain-input-control signal.

9. The system of claim 8 wherein the ET amplifier further comprises a variable power supply unit wherein the variable power supply unit is configured to operatively comprise the drain-input generation circuit.

10. The system of claim 9 wherein the drain-input generation circuit is a DC-to-DC converter.

11. The system of claim 10 wherein the DC-to-DC converter is fabricated using one of:

a) silicon on sapphire (SOS) technology, and b) silicon on insulator (SOI) technology.

12. The system of claim 9 wherein the amplifier unit further comprises a cascaded series of amplifiers operatively coupled in series, wherein each amplifier unit comprises a plurality of stacked transistors operatively coupled to a plurality of bias terminals adapted to receive the set of input-control signals.

13. The system in claim 12 wherein the cascaded series of amplifiers comprises a driver amplifier and a final amplifier, each comprising a drain terminal in correspondence of an output transistor.

14. The system of claim 13 wherein the drain-input generation circuit provides the drain-input-control signal to the driver amplifier and to the final amplifier.

15. The system of claim 14 wherein the drain-input generation circuit provides isolated drain-input-control signals to each of the driver amplifier and the final amplifier.

16. The system of claim 14 further comprising an isolation filter, wherein the isolation filter is inserted within a conduction path between the drain terminal of the driver amplifier and the drain terminal of the final amplifier.

17. The system of claim 16 wherein the isolation filter is configured to pass a DC signal and a signal at a frequency of the envelope signal.

18. The system of claim 16 wherein the isolation filter comprises an inductor in parallel with a capacitor.

19. The system of claim 13 further comprising a second drain-input generation circuit, such as each of the two drain-input generation circuits provides an independent drain-input-control signal to each of the driver amplifier and the final amplifier.

20. The system of claim 19 further comprising a second variable power supply unit comprising the second drain-input generation circuit.

21. The system of claim 12 or claim 13 further comprising a frequency selective filter operatively coupled in series between an output terminal of an amplifier of the cascaded series of amplifiers and an input terminal of a following amplifier.

22. The system of claim 21 wherein the frequency selective filter is configured to attenuate a signal at a frequency of the envelope signal.

23. The system of claim 22 wherein the frequency selective filter is a notch filter.

24. The system of claim 9 further comprising a transceiver unit configured to generate the RF input signal from a baseband data, wherein the combination of the transceiver unit, the variable power supply unit and the amplifier unit is configured to operatively comprise the envelope detection circuit, the gate-waveform generation circuit, the drain-waveform generation circuit, and the gate-input generation circuit.

25. The system of claim 24 wherein the transceiver unit is further configured to operatively comprise at least one of:

a) the drain-waveform generation circuit, b) the gate-waveform generation circuit;

c) the gate-input generation circuit, and d) the envelope detection circuit.

26. The system of claim 24 wherein the variable power supply unit is further configured to operatively comprise at least one of:

a) the drain-waveform generation circuit, b) the gate-waveform generation circuit;

c) the gate-input generation circuit, and d) the envelope detection circuit.

27. The system of claim 12 wherein the amplifier unit is further configured to operatively comprise at least one of:

a) the drain-waveform generation circuit, b) the gate-waveform generation circuit;

c) the gate-input generation circuit, and d) the envelope detection circuit.

28. The system of claim 24 wherein the set of operating parameters further comprises minimizing thermal memory effect of the amplifier unit.

29. The system of claim 24 wherein the waveform generation circuit further comprises circuitry configured to predict a temperature of the amplifier unit based on the RF input signal and provide a correction based on said predicted temperature such as said correction is combined with an output of the waveform generation circuit to further optimize response of the amplifier.

30. The system according to claim 1 wherein the ET amplifier further comprises a temperature detection circuit adapted to provide temperature data in correspondence of the operating temperature of the ET amplifier to the control circuit, and wherein the control circuit is adapted to further affect the response of the ET amplifier based on the operating temperature.

31. The system according to claim 1 wherein the ET amplifier further comprises a Non-Volatile RAM unit comprising characteristic data of the ET amplifier, and wherein the control circuit is adapted to access said characteristic data.

32. The system according to claim 31 wherein the characteristic data comprised within the Non-Volatile RAM is used to calibrate a target device integrating the ET amplifier.

33. The system according to any of claim 9, 14 or 20, wherein the ET amplifier is monolithically integrated.

34. The system according to claim 33 wherein an insulated silicon on sapphire (SOS) fabrication or an insulated silicon on insulator (SOI) fabrication technology is used.

35. A method for generating control signals to affect operation of an ET amplifier based on a desired response, the method comprising:

providing an ET amplifier configured to receive a drain control signal and a plurality of gate control signals;

generating the drain control signal based on an envelope signal of an RF input to the ET amplifier;

correlating a response of the ET amplifier with the plurality of gate control signals and the drain control signal;

generating a correlation table based on the obtained correlation;

selecting operating parameters for a desired response of the ET amplifier;

using the correlation table to generate a mapping table between the drain control signal and the gate control signals for the desired response;

implementing control circuitry adapted to generate the gate control signals from the drain control signal using the mapping table, and

affecting operation of the ET amplifier by feeding the drain control signal and the mapped gate control signals generated by the control circuitry to the ET amplifier.

36. The method of claim 35 wherein selecting of the operating parameters is based on at least one of:

a) maximizing linearity, b) maximizing efficiency, c) minimizing adjacent channel leakage ratio (ACLR), d) minimizing memory effects, and e) adjusting output power level.

37. The method of claim 35 wherein generating of the gate control signals comprises at least one of:

a) using memory based lookup tables, b) using analog circuitry comprising op-amps, and c) using digital circuitry.

38. The method of claim 35 wherein implementing of the control circuitry comprises at least one of:

a) operatively fitting the entirety of the control circuitry within the ET amplifier, and b) operatively fitting a portion of the control circuitry within the ET amplifier.

39. The method of claim 35 further comprising correlating the response of the ET amplifier with a change in one or more operating conditions of the amplifier unit, and further affecting operation of the amplifier by using said correlation.

40. The method of claim 39 wherein the one or more operating conditions comprises of a change in temperature.

41. The method of claim 35 wherein the ET amplifier further comprises a Non-Volatile RAM containing the mapping table of the ET amplifier.

42. A method for increasing stability in an amplifying arrangement, the method comprising:

providing a first ET amplifier;

providing a second ET amplifier;

serially coupling the first ET amplifier to the second ET amplifier, the first ET amplifier configured to receive an input signal of the amplifying arrangement and the second ET amplifier configured to output an output signal of the amplifying arrangement;

providing an ET power supply (ETPS) configured to supply a common power to a first power supply terminal of the first ET amplifier and to a second power supply terminal of the second ET amplifier;

modulating the common power in correspondence of an envelope signal of the input signal to the first ET amplifier;

inserting a filter in a conduction path between the first power supply terminal and the second power supply terminal;

based on the inserting, attenuating an undesired coupling between the first ET amplifier and the second ET amplifier;

based on the attenuating, increasing stability of the amplifying arrangement, such as to reduce oscillation at the output signal of the amplifying arrangement.

43. A method for reducing distortion in an amplifying arrangement, the method comprising:

providing a first ET amplifier configured to output an amplified input signal at a first output terminal, the input signal being fed to a first input terminal;

providing a second ET amplifier configured to receive an input signal at a second input terminal;

serially coupling the first ET amplifier to the second ET amplifier, the first ET amplifier configured to receive an input signal to the amplifying arrangement, the second ET amplifier configured to output an output signal of the amplifying arrangement;

providing an ET power supply (ETPS) configured to supply power to the first ET amplifier and to the second ET amplifier;

modulating the power in correspondence of an envelope signal of the input signal to the amplifying arrangement;

inserting a filter in a conduction path between the first output terminal and the second input terminal;

based on the inserting, attenuating an undesired coupling between the first ET amplifier and the second ET amplifier;

based on the attenuating, reducing distortion at the output signal of the amplifying arrangement.