METHOD AND SYSTEM FOR ASYNCHRONOUS DIE OPERATIONS IN A NON-VOLATILE MEMORY

• US 20140185376A1
• Filed: 03/14/2013
• Published: 07/03/2014
• Est. Priority Date: 12/31/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Sinclair, Alan Welsh, Thomas, Nicholas James, Wright, Barry
• Granted Patent: US 9,734,911 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A mass storage memory system and method of operation is disclosed. The memory includes an interface adapted to receive data from a host, a plurality of flash memory die and a controller, where the controller is configured to receive a first command and read or write data synchronously across the plurality of die based on a first command, and to receive a second command and read or write data asynchronously and independently in each die based on a second command. The controller may program data in a maximum unit of programming for an individual one of the plurality of flash memory die. The controller may be a plurality of controllers each configured to select which die of an exclusive subset of die to write data based on characteristics of the die in the subset. The plurality of die may be multi-layer, and multi-partition per layer, flash memory die.

Claims

1. A mass storage memory system, comprising:

an interface adapted to receive data from a host system;

a plurality of flash memory die; and

a controller in communication with the interface and the plurality of flash memory die, the controller configured to;

in response to receiving a first request from the host system, read or write data fully in parallel in the plurality of flash memory die; and

in response to receiving a second request from the host, read or write data independently and asynchronously with concurrent operations in each of the plurality of flash memory die.

2. The mass storage memory system of claim 1, wherein the controller is configured to manage data in an amount equal to a maximum unit of programming for an individual one of the plurality of flash memory die.

3. The mass storage memory system of claim 2, wherein the controller is configured to select a die within which to write received data based on a criteria independent of a host LBA address of the received data.

4. The mass storage memory system of claim 3, wherein the criteria comprises a die having a shortest pending data write queue.

5. The mass storage memory system of claim 3, wherein each of at least a portion of the plurality of flash memory die comprises:

a plurality of layers each having a plurality of memory blocks, wherein a first layer comprises a first bit-per-cell data capacity and a second layer comprises a second bit-per-cell capacity that is greater than the first bit-per-cell capacity; and

a plurality of partitions in each of the plurality of layers, wherein each programmed memory block in the plurality of memory blocks in a layer is exclusively classified as being in a respective one of the plurality of partitions.

6. The mass storage memory system of claim 5, wherein the controller is configured to identify a data type associated with received data from the host system and to select a die based on a number of outstanding transactions for the identified data type.

7. The mass storage memory system of claim 5, wherein the controller is configured to select a die having a lowest logical fullness.

8. The mass storage memory system of claim 2, wherein the controller comprises a plurality of controllers, the plurality of die are connected in groups to a respective one of a plurality of control channels and each of the plurality of controllers is only in communication with a group of the plurality of flash memory die on a respective one of the plurality of control channels.

9. The mass storage memory system of claim 8, wherein each of the plurality of controllers is configured to manage data associated with a respective predetermined unique host LBA address range.

10. The mass storage memory system of claim 9, wherein each of the plurality of controllers is configured to independently select a die connected to its respective control channel for writing received data independently of each other of the plurality of controllers.

11. A method of managing data comprising:

in a mass storage memory system having an interface adapted to receive data from a host system, a plurality of flash memory die, and a controller in communication with the interface and the plurality of flash memory die, the controller;

in response to receiving a first request from the host system, reading or writing data fully in parallel in the plurality of flash memory die; and

in response to receiving a second request from the host, reading or writing data independently and asynchronously with concurrent operations in each of the plurality of flash memory die.

12. The method of claim 11, further comprising the controller managing data writes in an amount equal to a maximum unit of programming for an individual one of the plurality of flash memory die.

13. The method of claim 11, further comprising the controller selecting a die within which to write received data based on criteria independent of a host LBA address of the received data.

14. The method of claim 13, wherein the criteria comprises a die having a shortest pending data write queue.

15. The method of claim 13, wherein each of at least a portion of the plurality of flash memory die comprises:

a plurality of layers each having a plurality of memory blocks, wherein a first layer comprises a first bit-per-cell data capacity and a second layer comprises a second bit-per-cell capacity that is greater than the first bit-per-cell capacity; and

a plurality of partitions in each of the plurality of layers, wherein each programmed memory block in the plurality of memory blocks in a layer is exclusively classified as being in a respective one of the plurality of partitions; and

wherein the controller interleaves copying of previously stored data between layers with writing of received host data.

16. The method claim 15, further comprising the controller:

identifying a data type associated with received data from the host system; and

selecting a die based on a number of outstanding transactions for the identified data type.

17. The method of claim 15, further comprising the controller selecting the die within which to write received data based on a lowest logical fullness in the plurality of flash memory die.

18. The method of claim 12, wherein the controller comprises a plurality of controllers, the plurality of die are connected in groups to a respective one of a plurality of control channels and each of the plurality of controllers is only in communication with a group of the plurality of flash memory die on a respective single one of the plurality of control channels, wherein the method further comprises:

receiving at each of the plurality of controllers only data associated with a respective predetermined unique host logical block address range.

19. The method of claim 18, further comprising each of the plurality of controllers independently selecting a die connected to its respective control channel for writing received data independently of each other of the plurality of controllers.