METHODS OF COPYING A PAGE IN A MEMORY DEVICE AND METHODS OF MANAGING PAGES IN A MEMORY SYSTEM

• US 20140185395A1
• Filed: 10/15/2013
• Published: 07/03/2014
• Est. Priority Date: 01/03/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seong-Young Seo
• Inventors: Seo, Seong-Young
• Granted Patent: US 9,076,514 B2
• Time in Patent Office: Days
• US Class Current: 365/189.17
• CPC Class Codes: G11C 2207/2236 Copy
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A method of copying a page in a memory device having a plurality of memory blocks and a plurality of sets of bit lines is disclosed, wherein each of the plurality of memory blocks includes a plurality of pages, and each set of bit lines corresponds to a respective memory block, wherein first bit lines of a source memory block that includes a source page are respectively coupled to second bit lines of a target memory block that includes a target page. The method includes disconnecting between the first bit lines of thea source memory block including a source page and from the second bit lines of a the target memory block including a target page; transferring data stored in the source page to the first bit lines of the source memory block; transferring the data from the first bit lines of the source memory block to the second bit lines of the target memory block; and writing the data transferred to the second bit lines of the target memory block into the target page.

Claims

1. A method of copying a page in a memory device having a plurality of memory blocks and a plurality of sets of bit lines, each of the plurality of memory blocks including a plurality of pages, and each set of bit lines corresponding to a respective memory block, wherein first bit lines of a source memory block that includes a source page are respectively coupled to second bit lines of a target memory block that includes a target page, the method comprising:

disconnecting the first bit lines of the source memory block from the second bit lines of the target memory block;

transferring data stored in the source page to the first bit lines of the source memory block;

transferring the data from the first bit lines of the source memory block to the second bit lines of the target memory block; and

writing the data transferred to the second bit lines of the target memory block into the target page.

2. The method of claim 1, wherein disconnecting the first bit lines of the source memory block from the second bit lines of the target memory block includes:

disconnecting between the first bit lines of the source memory block and bit lines of memory blocks adjacent to the source memory block.

3. The method of claim 1, wherein transferring the data stored in the source page to the first bit lines of the source memory block includes:

activating a word line of the source page; and

activating a sense amplifier of the source memory block to amplify voltages of the first bit lines of the source memory block.

4. The method of claim 1, wherein, in the case that the target memory block is adjacent to the source memory block, transferring the data from the first bit lines of the source memory block to the second bit lines of the target memory block includes:

disconnecting the second bit lines of the target memory block from bit lines of a memory block adjacent to the target memory block in an opposite direction of the source memory block;

turning off an equalizer of the target memory block; and

connecting between the first bit lines of the source memory block and the second bit lines of the target memory block.

5. The method of claim 4, wherein writing the data transferred to the second bit lines of the target memory block into the target page includes:

activating a word line of the target page.

6. The method of claim 5, further comprising:

precharging the first bit lines of the source memory block and the second bit lines of the target memory block after writing the data transferred to the second bit lines of the target memory block into the target page; and

connecting the second bit lines of the target memory block to the first bit lines of the source memory block and to the bit lines of the memory block adjacent to the target memory block in the opposite direction of the source memory block.

7. The method of claim 1, wherein, in the case that at least one memory block is located between the target memory block and the source memory block, transferring the data from the first bit lines of the source memory block to the second bit lines of the target memory block includes:

disconnecting the second bit lines of the target memory block from bit lines of a memory block adjacent to the target memory block in an opposite direction of the source memory block;

turning off equalizers of memory blocks located between the target memory block and the source memory block and an equalizer of the target memory block; and

connecting the first bit lines of the source memory block and bit lines of a memory block adjacent to the source memory block and in between the source memory block and the target memory block.

8. The method of claim 7, wherein writing the data transferred to the second bit lines of the target memory block into the target page includes:

activating a word line of the target page;

disconnecting the second bit lines of the target memory block from the bit lines of the memory block adjacent to the target memory block and in between the source memory block and the target memory block;

precharging bit lines of memory blocks, which are located between the target memory block and the source memory block and are not adjacent to the target memory block, and precharging the first bit lines of the source memory block;

activating a sense amplifier of the target memory block to amplify voltages of the second bit lines of the target memory block; and

activating the word line of the target page.

9. The method of claim 8, further comprising:

precharging the second bit lines of the target memory block and the bit lines of the memory block adjacent to the target memory block and in between the source memory block and the target memory block after writing the data transferred to the second bit lines of the target memory block into the target page; and

connecting between bit lines of adjacent memory blocks.

10. The method of claim 1, further comprising:

precharging bit lines of the plurality of memory blocks and connecting between bit lines of adjacent memory blocks before disconnecting between the first bit lines of the source memory block and the second bit lines of the target memory block.

11. The method of claim 1, wherein a connection between bit lines of adjacent memory blocks is controlled by an isolation transistor that turns on in response to an isolation control signal.

12. A method of managing pages in a memory system having a memory controller and a memory device, the memory device including a plurality of memory blocks, the method comprising:

providing a page copy command, a source address and a target address from the memory controller to the memory device; and

performing, in the memory device, a page copy operation, which copies data stored in a source page corresponding to the source address to a target page corresponding to the target address through bit lines of a source memory block including the source page and bit lines of a target memory block including the target page, in response to the page copy command.

13. The method of claim 12, wherein copying the data stored in the source page to the target page includes:

disconnecting between the bit lines of the source memory block and the bit lines of the target memory block;

transferring the data stored in the source page to the bit lines of the source memory block;

connecting between the bit lines of the source memory block and the bit lines of the target memory block

transferring the data from the bit lines of the source memory block to the bit lines of the target memory block; and

writing the data transferred to the bit lines of the target memory block into the target page.

14. The method of claim 13, wherein disconnecting includes opening a set of switches between the bit lines of the source memory block and the bit lines of the target memory block, and the connecting includes closing the set of switches between the bit lines of the source memory block and the bit lines of the target memory block.

15. The method of claim 12, wherein the memory device finishes the page copy operation in a predetermined time interval from a time at which the memory device receives the page copy command, the source address and the target address from the memory controller, and further comprising:

selecting as the target memory block a memory block among the plurality of memory blocks in which a number of pages that store data is greater than a number of pages that do not store data;

determining first through n-th target addresses corresponding to the pages that do not store data in the target memory block, n being a positive integer;

determining first through n-th source addresses corresponding to pages that store data in a memory block in which a number of the pages that store data is smaller than a number of pages that do not store data;

providing the page copy command n-times together with a respective pair of a k-th source address and k-th target address consecutively in accordance with the predetermined time interval from the memory controller to the memory device, k being a positive integer smaller than or equal to n;

providing a refresh command for the target memory block from the memory controller to the memory device; and

performing, in the memory device, a refresh operation, which refreshes pages included in the target memory block, in response to the refresh command.

16. A memory system, comprising:

a controller; and

a memory device coupled to the controller, the memory device including;

a plurality of blocks of memory cells including at least a first block and a second block having no blocks therebetween, each block of the plurality of blocks including a plurality of pages of memory cells, wherein the first block includes a first plurality of pages coupled to a plurality of first bit lines, and the second block includes a second plurality of pages coupled to a plurality of second bit lines; and

a plurality of first switches coupled respectively between the plurality of first bit lines and the plurality of second bit lines,

wherein the controller is configured to copy data stored in a first page of the first plurality of pages to a second page of the second plurality of pages by controlling the plurality of first switches.

17. The memory system of claim 16, wherein the controller is configured to perform a procedure of opening and closing the plurality of first switches in order to copy the data stored in the first page to the second page.

18. The memory system of claim 17, wherein the controller is configured to:

open the plurality of first switches to disconnect the plurality of first bit lines from the plurality of second bit lines;

transfer data stored in the first page to the plurality of first bit lines;

close the plurality of first switches to connect the plurality of first bit lines to the plurality of second bit lines;

transfer the data from the plurality of first bit lines to the plurality of second bit lines; and

write the data transferred to the plurality of second bit lines to the second page.

19. The memory system of claim 18, wherein the memory device further includes:

at least a third block of memory cells including a third plurality of pages of memory cells coupled to a plurality of third bit lines and at least a fourth block of memory cells including a fourth plurality of pages of memory cells coupled to a plurality of fourth bit lines, wherein the first block of memory cells are disposed between the second block of memory cells and the third block of memory cells, and the second block of memory cells are disposed between the first block of memory cells and the fourth block of memory cells;

a plurality of second switches coupled respectively between the plurality of first bit lines and the plurality of third bit lines; and

a plurality of third switches coupled respectively between the plurality of second bit lines and the plurality of fourth bit lines.

20. The memory system of claim 19, wherein the controller is further configured to:

open the plurality of second switches prior to transferring the data stored in the first page to the plurality of first bit lines;

open the plurality of third switches prior to transferring the data from the plurality of first bit lines to the plurality of second bit lines; and

close the plurality of second switches and the plurality of third switches after writing the data transferred to the plurality of second bit lines to the second page.