Signal Delay Estimator with Absolute Delay Amount and Direction Estimation

• US 20140185723A1
• Filed: 12/27/2012
• Published: 07/03/2014
• Est. Priority Date: 12/27/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Mobile Communications GmbH (Intel Corporation)
• Inventors: Belitzer, Alexander
• Granted Patent: US 8,781,049 B1
• Time in Patent Office: Days
• US Class Current: 375/354
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H04B 17/104 of other parameters, e.g. DC offset, delay or propagation times
• CPC Class Codes: H04L 7/0033 Correction by delay
• CPC Class Codes: H04L 7/0041 Delay of data signal
• CPC Class Codes: H04L 7/0079 Receiver details
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A signal delay estimator includes an adjustable delay element for delaying a first signal to obtain a delayed first signal, a delay amount estimator for estimating a delay amount between the delayed first signal and a second signal that is similar and delayed relative to the first signal, and a leading signal determiner for determining whether the delayed first signal leads the second signal or vice versa, and for generating a corresponding binary signal. A selective inverter is provided for selectively inverting the delay amount depending on the binary signal. The signal delay estimator also includes a feedback element to the adjustable delay element for controlling a delay based on an output of the selective inverter. Another exemplary signal delay estimator includes a closed control loop with an adjustable delay element and separate first and second processing paths for absolute delay amount and delay direction, respectively.

Claims

1. A signal delay estimator, comprising:

an adjustable delay element for delaying a first signal to obtain a delayed first signal;

a delay amount estimator configured to estimate a delay amount between the delayed first signal and a second signal that is similar and delayed relative to the first signal;

a leading signal determiner configured to determine whether the delayed first signal leads the second signal or vice versa, and generate a corresponding binary signal based thereon;

a selective inverter configured to selectively invert the delay amount based on the binary signal; and

a feedback element to the adjustable delay element configured to control a delay of the adjustable delay element based on an output of the selective inverter.

2. The signal delay estimator according to claim 1, wherein the leading signal determiner comprises:

a first input configured to receive an error signal corresponding to a delay between the delayed first signal and the second signal;

a second input configured to receive the second signal;

a slope detector configured to detect whether one of the first signal and the second signal has a slope greater than zero, and output, as a slope detector output signal, the error signal if the slope is greater than zero and otherwise output a zero signal;

an error integrator configured to integrate the slope detector output signal; and

an integration result evaluator configured to set the corresponding binary signal to a first value if an integration result is positive, and to a second, different value if the integration result is negative.

3. The signal delay estimator according to claim 2, wherein the error integrator is configured to integrate the slope detector output signal over a time interval.

4. The signal delay estimator according to claim 3, wherein the time interval is variable, and wherein the signal delay estimator further comprises a time interval adjuster configured to set a relatively short time interval if a bandwidth of the first signal is greater than a threshold and a relatively long time interval if a bandwidth of the first signal is less than the threshold.

5. The signal delay estimator according to claim 2, wherein at least one of the error signal and the slope detector output signal is a time discrete signal, and wherein the error integrator is configured to sum the slope detector output signal over a plurality of samples.

6. The signal delay estimator according to claim 1, wherein the leading signal determiner comprises:

a first input configured to receive an error signal corresponding to a delay between the delayed first signal and the second signal;

a second input configured to receive the second signal;

a slope detector configured to detect whether one of the first signal and the second signal has a slope less than zero, and output, as a slope detector output signal, the error signal if the slope is less than zero and otherwise output a zero signal;

an error integrator configured to integrate the slope detector output signal; and

an integration result evaluator configured to set the corresponding binary signal to a first value if an integration result is positive and to a second, different value of the integration result is negative.

7. The signal delay estimator according to claim 1, wherein the delay amount estimator comprises:

an error signal determiner configured to determine an error signal corresponding to a delay between the delayed first signal and the second signal; and

an absolute value error integrator configured to integrate an absolute value of the error signal over an absolute value integration time interval, wherein the absolute value error integrator outputs the delay amount.

8. The signal delay estimator according to claim 7, wherein the error signal determiner of the delay amount estimator comprises an output configured to provide the error signal to the leading signal determiner.

9. The signal delay estimator according to claim 1, wherein the selective inverter comprises a non-inverting path for the delay amount, an inverting path for the delay amount, and a multiplexer having the non-inverting path and the inverting path as inputs, wherein the multiplexer is configured to select one of the non-inverting path and the inverting path as an active input as a function of the binary signal provided by the leading signal determiner.

10. The signal delay estimator according to claim 1, further comprising an integrator configured to integrate the output of the selective inverter.

11. The signal delay estimator according to claim 1, further comprising a scaling element configured to scale the output of the selective inverter with a loop gain.

12. The signal delay estimator according to claim 11, further comprising a loop gain adjuster configured to set the loop gain to follow a decreasing gain profile.

13. The signal delay estimator according to claim 11, further comprising a loop gain adjuster configured to set the loop gain based on an estimation of a noise portion within the delay amount.

14. The signal delay estimator according to claim 1, further comprising at least one DC remover configured to remove a DC component of at least one of the first signal and the second signal.

15. The signal delay estimator according to claim 1, wherein the adjustable delay element comprises an integer delay portion and a fractional delay portion relative to a sampling rate of the first and second signals.

16. A signal delay estimator comprising:

a closed control loop comprising an adjustable delay element as control element and separate first and second processing paths configured to ascertain an absolute delay amount and a delay direction, respectively, wherein the delay direction indicates whether a delayed version of a first signal leads a second signal, or vice versa, and wherein the second signal is similar and delayed relative to the first signal,

wherein the second processing path for the delay direction comprises;

a slope-selective error signal integrator configured to integrate an error signal between the delayed first signal and the second signal if a slope of the second signal is positive, and

an integration result evaluator configured to evaluate whether an integration result provided by the slope-selective error signal integrator is greater than a threshold value and set a binary signal to a first value or a second value based on a result of the evaluation.

17. A mobile communication device, comprising:

an antenna port;

a digital baseband processor;

an RF-frontend coupled to the antenna port and to the digital baseband processor; and

a signal delay estimator associated with the digital baseband processor and the RF-frontend, comprising;

an adjustable delay element configured to delay a first signal to obtain a delayed first signal;

a delay amount estimator configured to estimate a delay amount between the delayed first signal and a second signal that is similar and delayed relative to the first signal;

a leading signal determiner configured to determine whether the delayed first signal leads the second signal or vice versa, and generate a corresponding binary signal;

a selective inverter configured to selectively invert the delay amount based on the binary signal; and

a feedback element to the adjustable delay element configured to control a delay based on an output of the selective inverter.

18. The mobile communication device according to claim 17, wherein the first signal is provided by the digital baseband processor and the second signal is provided by the RF-frontend to the antenna port based on the first signal.

19. A mobile communication device, comprising:

an antenna port;

a digital baseband processor;

an RF-frontend coupled to the antenna port and to the digital baseband processor; and

a signal delay estimator associated with the digital baseband processor and the RF-frontend, comprising;

a closed control loop comprising an adjustable delay element a as control element and separate first and second processing paths configured to ascertain an absolute delay amount and a delay direction, respectively, wherein the delay direction indicates whether a delayed version of a first signal leads a second signal, or vice versa, and wherein the second signal is similar and delayed relative to the first signal,

wherein the second processing path for the delay direction comprises;

a slope-selective error signal integrator configured to integrate an error signal between the delayed first signal and the second signal if a slope of the second signal is positive, and

an integration result evaluator configured to evaluate whether an integration result provided by the slope-selective error signal integrator is greater than a threshold value and set a binary signal to a first value or a second value based on a result of the evaluation.

20. A method for estimating a delay between a first signal and a similar second signal, the method comprising:

delaying the first signal by an adjustable delay to obtain a delayed first signal;

estimating a delay amount between the delayed first signal and the second signal;

determining whether the delayed first signal leads the second signal or vice versa and generating a corresponding binary signal based thereon;

selectively inverting the delay amount based on the binary signal to obtain a conditionally inverted delay amount; and

adjusting the adjustable delay used for delaying the first signal based on the conditionally inverted delay amount.

21. The method according to claim 20, wherein determining whether the first signal leads the second signal or vice versa comprises:

detecting whether one of the first signal and the second signal has a slope greater than zero;

determining an error signal between the delayed first signal and the second signal;

generating a slope detection signal if the slope is greater than zero and otherwise a zero signal;

integrating the error signal if the slope is greater than zero; and

setting the binary signal to a first value if an integration result is positive and to a second value if the integration result is negative.

22. The method according to claim 21, wherein the error signal is integrated over a time interval and then evaluated as to whether the integration result is positive or negative.

23. The method according to claim 22, further comprising:

setting a relatively short time interval as the time interval if a bandwidth of the first signal is greater than a threshold and setting a relatively long time interval as the time interval if the bandwidth of the first signal is less than the threshold.

24. The method according to claim 21, wherein at least one of the error signal and the slope detection signal is a time discrete signal, and wherein integrating the error signal comprises summing the error signal over a plurality of samples.

25. The method according to claim 20, further comprising:

setting a loop gain based on one of a decreasing loop gain and an estimation of a noise portion within the delay amount; and

scaling the conditionally inverted delay amount with the loop gain.

26. A method for estimating a delay between a first signal and a second signal, the method comprising:

delaying the first signal by an adjustable delay to obtain a delayed first signal;

determining an error signal between the delayed first signal and the second signal;

integrating the error signal if a slope of one of the first signal, the delayed first signal, and the second signal is positive; and

evaluating whether an integration result is greater than a threshold value and setting a binary signal to a first value or a second value depending on a result of the evaluation.